SLPS264D October   2010  – May 2015 CSD86330Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Power Loss Curves
    2. 6.2 Safe Operating Curves (SOA)
    3. 6.3 Normalized Curves
    4. 6.4 Calculating Power Loss and SOA
      1. 6.4.1 Design Example
      2. 6.4.2 Calculating Power Loss
      3. 6.4.3 Calculating SOA Adjustments
  7. 7Recommended PCB Design Overview
    1. 7.1 Electrical Performance
    2. 7.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q3D Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQZ|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
Voltage range VIN to PGND –0.8 25 V
TG to TGR –8 10 V
BG to PGND –8 10 V
Pulsed Current Rating, IDM 60 A
Power Dissipation, PD 6 W
Avalanche Energy EAS Sync FET, ID = 65 A, L = 0.1 mH 211 mJ
Control FET, ID = 42 A, L = 0.1 mH 88
Operating junction, TJ –55 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
Gate drive voltage, VGS 4.5 8 V
Input supply voltage, VIN 22 V
Switching frequency, fSW CBST = 0.1 µF (min) 200 1500 kHz
Operating current 20 A
Operating temperature, TJ 125 °C

5.3 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (Min Cu)(2) 135 °C/W
Junction-to-ambient thermal resistance (Max Cu)(2)(1) 73
RθJC Junction-to-case thermal resistance (Top of package)(2) 29
Junction-to-case thermal resistance (PGND Pin)(2) 2.5
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.
(2) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches× 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.4 Power Block Performance

TA = 25° (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Loss, PLOSS(1) VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 15 A,
fSW = 500 kHz,
LOUT = 1 µH, TJ = 25ºC
1.9 W
VIN Quiescent Current, IQVIN TG to TGR = 0 V
BG to PGND = 0 V
10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 µA 25 25 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 20 V 1 1 µA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = +10 / –8 100 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 µA 0.9 1.4 2.1 0.9 1.1 1.6 V
ZDS(on) Effective AC On-Impedance VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 15 A,
ƒSW = 500 kHz,
LOUT = 1 µH
8.8 3.3
gƒs Transconductance VDS = 15 V, IDS = 14 A 52 82 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance(1) VGS = 0 V, VDS = 12.5 V,
ƒ = 1 MHz
710 920 1280 1660 pF
COSS Output Capacitance(1) 350 455 680 880 pF
CRSS Reverse Transfer Capacitance(1) 18 23 38 49 pF
RG Series Gate Resistance(1) 1.5 3.0 1.2 2.4 Ω
Qg Gate Charge Total (4.5 V)(1) VDS = 12.5 V,
IDS = 14 A
4.8 6.2 9.2 12 nC
Qgd Gate Charge - Gate-to-Drain 0.9 1.6 nC
Qgs Gate Charge - Gate-to-Source 1.6 2.1 nC
Qg(th) Gate Charge at Vth 0.9 1.2 nC
QOSS Output Charge VDS = 15.5 V, VGS = 0 V 7.2 13.6 nC
td(on) Turn On Delay Time VDS = 12.5 V, VGS = 4.5 V,
IDS = 14 A, RG = 2 Ω
4.9 5.3 ns
tr Rise Time 7.5 6.3 ns
td(off) Turn Off Delay Time 8.5 15.8 ns
tƒ Fall Time 1.9 4.2 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 14 A, VGS = 0 V 0.85 1 0.8 1 V
Qrr Reverse Recovery Charge Vdd = 15.5 V, IF = 14 A,
di/dt = 300 A/µs
3.9 7.3 nC
trr Reverse Recovery Time 13.9 19 ns
(1) Specified by design
CSD86330Q3D M0205-01_LPS264.gif
Max RθJA = 76°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD86330Q3D M0206-01_LPS264.gif
Max RθJA = 140°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.2 V, LOUT = 1.0 µH, IOUT = 20 A, TJ = 125°C, unless stated otherwise.
CSD86330Q3D G001_LPS264.gif
Figure 1. Power Loss vs Output Current
CSD86330Q3D G003_LPS264.gif
Figure 3. Safe Operating Area – PCB Vertical Mount(1)1
CSD86330Q3D G002_LPS264.gif
Figure 2. Power Loss vs Temperature
CSD86330Q3D G004_LPS264.gif
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)1
CSD86330Q3D G005_LPS264.gif
Figure 5. Typical Safe Operating Area(1)1
1. The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section for detailed explanation.
CSD86330Q3D G006_LPS264.gif
Figure 6. Normalized Power Loss vs Switching Frequency
CSD86330Q3D G008_LPS264.gif
Figure 8. Normalized Power Loss vs Output Voltage
CSD86330Q3D G007_LPS264.gif
Figure 7. Normalized Power Loss vs Input Voltage
CSD86330Q3D G009_LPS264.gif
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD86330Q3D G010_LPS264.gif
Figure 10. Control MOSFET Saturation
CSD86330Q3D G012_LPS264.gif
Figure 12. Control MOSFET Transfer
CSD86330Q3D G014_LPS264.gif
Figure 14. Control MOSFET Gate Charge
CSD86330Q3D G016_LPS264.gif
Figure 16. Control MOSFET Capacitance
CSD86330Q3D G018_LPS264.gif
Figure 18. Control MOSFET VGS(th)
CSD86330Q3D fig20.png
Figure 20. Control MOSFET RDS(on) vs VGS
CSD86330Q3D G022_LPS264.gif
Figure 22. Control MOSFET Normalized RDS(on)
CSD86330Q3D G024_LPS264.gif
Figure 24. Control MOSFET Body Diode
CSD86330Q3D G026_LPS264.gif
Figure 26. Control MOSFET Unclamped Inductive Switching
CSD86330Q3D G011_LPS264.gif
Figure 11. Sync MOSFET Saturation
CSD86330Q3D G013_LPS264.gif
Figure 13. Sync MOSFET Transfer
CSD86330Q3D G015_LPS264.gif
Figure 15. Sync MOSFET Gate Charge
CSD86330Q3D G017_LPS264.gif
Figure 17. Sync MOSFET Capacitance
CSD86330Q3D G019_LPS264.gif
Figure 19. Sync MOSFET VGS(th)
CSD86330Q3D fig21.png
Figure 21. Sync MOSFET RDS(on) vs VGS
CSD86330Q3D G023_LPS264.gif
Figure 23. Sync MOSFET Normalized RDS(on)
CSD86330Q3D G025_LPS264.gif
Figure 25. Sync MOSFET Body Diode
CSD86330Q3D G027_LPS264.gif
Figure 27. Sync MOSFET Unclamped Inductive Switching