SLPS283B September   2011  – February 2017 CSD87331Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Calculating Power Loss and SOA
        1. 6.2.1.1 Design Example
        2. 6.2.1.2 Calculating Power Loss
        3. 6.2.1.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Q3D Tape and Reel Information
      1. 9.3.1 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
PARAMETER CONDITIONS MIN MAX UNIT
Voltage VIN to PGND 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to TGR –8 10
BG to PGND –8 10
Pulsed current rating, IDM(2) 45 A
Power dissipation, PD 6 W
Avalanche energy, EAS Sync FET, ID = 42 A, L = 0.1 mH 88 mJ
Control FET, ID = 24 A, L = 0.1 mH 29
Operating junction, TJ –55 150 °C
Storage temperature, TSTG –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µs, Duty cycle ≤ 0.01%.

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
Gate drive voltage, VGS 4.5 8 V
Input supply voltage, VIN 27 V
Switching frequency, ƒSW CBST = 0.1 µF (min) 1500 kHz
Operating current 15 A
Operating temperature, TJ 125 °C

5.3 Power Block Performance(1)

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Power loss, PLOSS(1) VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 10 A, ƒSW = 500 kHz,
LOUT = 1 µH, TJ = 25°C 		1.3 W
VIN quiescent current, IQVIN TG to TGR = 0 V BG to PGND = 0 V 10 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5-V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(2) 149 °C/W
Junction-to-ambient thermal resistance (max Cu)(2)(1) 80
RθJC Junction-to-case thermal resistance (top of package)(2) 36 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 3.1
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET
MIN TYP MAX MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 30 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 µA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 1 2.1 0.8 1.2 V
ZDS(on) Effective AC on-impedance VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 10 A,
ƒSW = 500 kHz,
LOUT = 1 µH		 18 5.5 mΩ
gfs Transconductance VDS = 15 V, IDS = 8A 26 48 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 432 518 926 1110 pF
COSS Output capacitance 158 190 378 454 pF
CRSS Reverse transfer capacitance 7 9 24 30 pF
RG Series gate resistance 5.2 6.5 0.7 1.5 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
IDS = 8 A		 2.7 3.2 6.4 7.7 nC
Qgd Gate charge gate-to-drain 0.4 1.1 nC
Qgs Gate charge gate-to-source 0.9 1.5 nC
Qg(th) Gate charge at Vth 0.5 0.8 nC
QOSS Output charge VDS = 14 V, VGS = 0 V 3.6 7.7 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
IDS = 8 A, RG = 2 Ω		 3.4 3.8 ns
tr Rise time 4.5 4.7 ns
td(off) Turnoff delay time 7.4 11.2 ns
tf Fall time 1.3 2.4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 8 A, VGS = 0 V 0.85 1 0.85 1 V
Qrr Reverse recovery charge VDS = 14 V, IF = 8 A,
di/dt = 300 A/µs		 4 5.9 nC
trr Reverse recovery time 10 13 ns
CSD87331Q3D M0205-01_LPS264.gif
Max RθJA = 80°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD87331Q3D M0206-01_LPS264.gif
Max RθJA = 149°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 1 µH, IOUT = 15 A, TJ = 125°C, unless stated otherwise.
CSD87331Q3D graph01_LPS283.png
Figure 1. Power Loss vs Output Current
CSD87331Q3D graph03_LPS283.png Figure 3. Safe Operating Area – PCB Vertical Mount(1)1
CSD87331Q3D graph05_LPS283.png Figure 5. Typical Safe Operating Area(1)1
CSD87331Q3D graph02_LPS283.png
Figure 2. Power Loss vs Temperature
CSD87331Q3D graph04_LPS283.png Figure 4. Safe Operating Area – PCB Horizontal Mount(1)1
1. The typical power block system characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation section for detailed explanation.
CSD87331Q3D graph06_LPS283.png
Figure 6. Normalized Power Loss vs Switching Frequency
CSD87331Q3D graph08_LPS283.png
Figure 8. Normalized Power Loss vs Output Voltage
CSD87331Q3D graph07_LPS283.png
Figure 7. Normalized Power Loss vs Input Voltage
CSD87331Q3D graph09_LPS283.png
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87331Q3D graph10_LPS283.png
Figure 10. Control MOSFET Saturation
CSD87331Q3D graph12_LPS283.png
Figure 12. Control MOSFET Transfer
CSD87331Q3D graph14_LPS283.png
Figure 14. Control MOSFET Gate Charge
CSD87331Q3D graph16_LPS283.png
Figure 16. Control MOSFET Capacitance
CSD87331Q3D graph18_LPS283.png
Figure 18. Control MOSFET VGS(th)
CSD87331Q3D graph20_LPS283.png
Figure 20. Control MOSFET RDS(on) vs VGS
CSD87331Q3D graph22_LPS283.png
Figure 22. Control MOSFET Normalized RDS(on)
CSD87331Q3D graph24_LPS283.png
Figure 24. Control MOSFET Body Diode
CSD87331Q3D graph26_LPS283.png
Figure 26. Control MOSFET Unclamped Inductive Switching
CSD87331Q3D graph11_LPS283.png
Figure 11. Sync MOSFET Saturation
CSD87331Q3D graph13_LPS283.png
Figure 13. Sync MOSFET Transfer
CSD87331Q3D graph15_LPS283.png
Figure 15. Sync MOSFET Gate Charge
CSD87331Q3D graph17_LPS283.png
Figure 17. Sync MOSFET Capacitance
CSD87331Q3D graph19_LPS283.png
Figure 19. Sync MOSFET VGS(th)
CSD87331Q3D graph21_LPS283.png
Figure 21. Sync MOSFET RDS(on) vs VGS
CSD87331Q3D graph23_LPS283.png
Figure 23. Sync MOSFET Normalized RDS(on)
CSD87331Q3D graph25_LPS283.png
Figure 25. Sync MOSFET Body Diode
CSD87331Q3D graph27_LPS283.png
Figure 27. Sync MOSFET Unclamped Inductive Switching