SLPS405F March   2013  – March 2015 CSD87381P

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. 6.1.4.1 Design Example
        2. 6.1.4.2 Calculating Power Loss
        3. 6.1.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Recommended PCB Design Overview
      2. 7.1.2 Electrical Performance
      3. 7.1.3 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87381P Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87381P Embossed Carrier Tape Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to VSW –8 10
BG to PGND –8 10
IDM Pulsed Current Rating(2) 40 A
PD Power Dissipation(3) 4 W
EAS Avalanche Energy Sync FET, ID = 27, L = 0.1 mH 36 mJ
Control FET, ID = 20, L = 0.1 mH 20
TJ Operating Junction –55 150 °C
Tstg Storage Temperature Range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse Duration ≤50 µs, duty cycle ≤0.01
(3) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu

5.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VGS Gate Drive Voltage 4.5 8 V
VIN Input Supply Voltage 24 V
ƒSW Switching Frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating Current No Airflow 15 A
With Airflow (200 LFM) 20
With Airflow + Heat Sink 25
TJ Operating Temperature 125 °C

5.3 Power Block Performance

TA = 25° (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power Loss(1) VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 8 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25ºC 		1 W
IQVIN VIN Quiescent Current TG to TGR = 0 V
BG to PGND = 0 V 		10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu) (1) 184 °C/W
Junction-to-ambient thermal resistance (max Cu) (2)(1) 84
RθJC Junction-to-case thermal resistance (top of package) (1) 4.9
Junction-to-case thermal resistance (PGND pin) (1) 1.65
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 10 V 100 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.1 1.9 1 1.7 V
RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V, IDS = 8 A 15.7 18.9 7 8.4 mΩ
VGS = 8 V, IDS = 8 A 13.6 16.3 6.3 7.6
gƒs Transconductance VDS = 10 V, IDS = 8 A 40 89 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance (1) VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 434 564 1020 1320 pF
COSS Output Capacitance (1) 225 293 308 400 pF
CRSS Reverse Transfer Capacitance (1) 9.1 11.8 40 52 pF
RG Series Gate Resistance (1) 5 6.4 1.25 2.5 Ω
Qg Gate Charge Total (4.5 V) (1) VDS = 15 V,
IDS = 8 A		 3.9 5 8.9 11.5 nC
Qgd Gate Charge – Gate-to-Drain 0.9 2.5 nC
Qgs Gate Charge – Gate-to-Source 1.2 2 nC
Qg(th) Gate Charge at Vth 0.7 1.3 nC
QOSS Output Charge VDD = 12 V, VGS = 0 V 4.9 8.5 nC
td(on) Turn On Delay Time VDS = 15 V, VGS = 4.5 V,
IDS = 8 A, RG = 2 Ω		 6.7 7.9 ns
tr Rise Time 19.3 16.3 ns
td(off) Turn Off Delay Time 10.6 16.8 ns
tƒ Fall Time 3 2.9 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 8 A, VGS = 0 V 0.85 0.79 V
Qrr Reverse Recovery Charge Vdd = 15 V, IF = 8 A,
di/dt = 300 A/μs		 8 16 nC
trr Reverse Recovery Time 13 17 ns
(1) Specified by design
CSD87381P Thermal_max.gif
 Max RθJA = 84°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD87381P Thermal_Min.gif
 Max RθJA = 184°C/W when mounted on minimum pad area of 2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Characteristics

TJ = 125°C, unless stated otherwise. For Figure 3 and Figure 4, the Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
CSD87381P graph01_SLPS405F.png
Figure 1. Power Loss vs Output Current
CSD87381P graph03_SLPS405F.png
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87381P graph02_SLPS405F.png
Figure 2. Normalized Power Loss vs Temperature
CSD87381P graph04_SLPS405F.png
Figure 4. Typical Safe Operating Area
CSD87381P graph05_SLPS405F.png
Figure 5. Normalized Power Loss vs Switching Frequency
CSD87381P graph07_SLPS405F.png
Figure 7. Normalized Power Loss vs Output Voltage
CSD87381P graph06_SLPS405F.png
Figure 6. Normalized Power Loss vs Input Voltage
CSD87381P graph08_SLPS405F.png
Figure 8. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87381P graph09_SLPS405F.png
Figure 9. Control MOSFET Saturation
CSD87381P graph11_SLPS405F3.png
Figure 11. Control MOSFET Transfer
CSD87381P graph14_SLPS405F.png
Figure 13. Control MOSFET Gate Charge
CSD87381P graph15_SLPS405_revF.png
Figure 15. Control MOSFET Capacitance
CSD87381P graph17_SLPS405F.png
Figure 17. Control MOSFET VGS(th)
CSD87381P graph19_SLPS405F.png
Figure 19. Control MOSFET RDS(on) vs VGS
CSD87381P graph21_SLPS405F.png
Figure 21. Control MOSFET Normalized RDS(on)
CSD87381P graph23_SLPS405F.png
Figure 23. Control MOSFET Body Diode
CSD87381P graph25_SLPS405F2.png
Figure 25. Control MOSFET Unclamped Inductive Switching
CSD87381P graph10_SLPS405F.png
Figure 10. Sync MOSFET Saturation
CSD87381P graph12_SLPS405F.png
Figure 12. Sync MOSFET Transfer
CSD87381P graph04_LPS.png
Figure 14. Sync MOSFET Gate Charge
CSD87381P graph16_SLPS405_revF.png
Figure 16. Sync MOSFET Capacitance
CSD87381P graph18_SLPS405F.png
Figure 18. Sync MOSFET VGS(th)
CSD87381P graph20_SLPS405F.png
Figure 20. Sync MOSFET RDS(on) vs VGS
CSD87381P graph22_SLPS405F.png
Figure 22. Sync MOSFET Normalized RDS(on)
CSD87381P graph24_SLPS405F.png
Figure 24. Sync MOSFET Body Diode
CSD87381P graph26_SLPS405F.png
Figure 26. Sync MOSFET Unclamped Inductive Switching