SLPS598C May 2017 – January 2018 CSD88584Q5DC
CSD88584Q5DC was designed to operate up to 7-cell Li-Ion battery voltage applications ranging from 18 V to 32 V, typical 24 V. For 8s, input voltages between 32 V to 36 V, RC snubbers are required for each switch-node U, V, and W. To reduce ringing, refer to the Electrical Performance section. In an effort to simplify the design process, Texas Instruments has provided measured power loss performance curves over a variety of typical conditions.
Figure 1 plots the CSD88584Q5DC power loss as a function of load current. The measured power loss includes both input conversion loss and gate drive loss.
Equation 1 is used to generate the power loss curve:
The power loss measurements were made on the circuit shown in Figure 19, power block devices for legs U and V, PB1 and PB2 were disabled by shorting the CSD88584Q5DC high-side and low-side FETs gate-to-source terminals. Current shunt Iin_shunt provides Input current and Idd_SHUNT provides driver supply current measurements. The winding current is measured from the DC load. An averaging circuit provides switch node W equivalent RMS voltage.
The RMS current on the CSD88584Q5DC device depends on the motor winding current. For trapezoidal control, the MOSFET RMS current is calculated using Equation 2.
Taking into consideration system tolerances with the current measurement scheme, the inverter design needs to withstand a 20% overload current.
|Winding RMS Current (A)||CSD88584Q5DC IRMS (A)||Overload 120% × IRMS (A)|