SLPS584B December   2015  – December 2017 CSD95377Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering CSD95377Q4M and Gate Drivers
      2. 7.3.2 Undervoltage Lockout (UVLO) Protection
      3. 7.3.3 PWM Pin
      4. 7.3.4 SKIP# Pin
        1. 7.3.4.1 Zero Crossing (ZX) Operation
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 Safe Operating Area (SOA) Curves
      3. 8.3.3 Normalized Curves
      4. 8.3.4 Calculating Power Loss and SOA
        1. 8.3.4.1 Design Example
        2. 8.3.4.2 Calculating Power Loss
        3. 8.3.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

Two key system-level parameters can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description follows on how to address each parameter.

9.1.2 Electrical Performance

The CSD95377Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Take special care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of the CSD95377Q4M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 16). The example in Figure 16 uses 1 × 1-nF 0402, 25-V and 3 × 10-µF 1206, 25-V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power stage C5, C8, C6, and C19 should follow in order.
  • The bootstrap capacitor CBOOT 0.1-µF 0603, 16-V ceramic capacitor should be closely connected between BOOT and BOOT_R pins.
  • The switching node of the output inductor should be placed relatively close to the power stage CSD95377Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. (1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

1. Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

9.2 Layout Example

CSD95377Q4M Recomended_PCB_Layout.png Figure 16. Recommended PCB Layout (Top-Down View)

9.3 Thermal Considerations

The CSD95377Q4M has the ability to use the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 16 uses vias with a 10-mil drill hole and a 16-mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.