SLPS572 December   2015 CSD97396Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering CSD97396Q4M and Gate Drivers
      2. 7.3.2 Undervoltage Lockout (UVLO) Protection
      3. 7.3.3 PWM Pin
      4. 7.3.4 SKIP# Pin
        1. 7.3.4.1 Zero Crossing (ZX) Operation
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 SOA Curves
      3. 8.3.3 Normalized Curves
      4. 8.3.4 Calculating Power Loss and SOA
        1. 8.3.4.1 Design Example
        2. 8.3.4.2 Calculating Power Loss
        3. 8.3.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Community Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
VIN to PGND –0.3 30 V
VSW to PGND , VIN to VSW –0.3 30 V
VSW to PGND, VIN to VSW (<10 ns) –7 33 V
VDD to PGND –0.3 6 V
PWM, SKIP# to PGND –0.3 6 V
BOOT to PGND –0.3 35 V
BOOT to PGND (<10 ns) –2 38 V
BOOT to BOOT_R –0.3 6 V
BOOT to BOOT_R (duty cycle <0.2%) 8 V
PD Power dissipation 8 W
TJ Operating temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM)(1) ±1000 V
Charged device model (CDM)(2) ±500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VDD Gate drive voltage 4.5 5.5 V
VIN Input supply voltage (1) 24 V
IOUT Continuous output current VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH(2)		 30 A
IOUT-PK Peak output current(3) 65 A
ƒSW Switching frequency CBST = 0.1 µF (min) 2000 kHz
On-time duty cycle 85%
Minimum PWM on-time 40 ns
Operating temperature –40 125 °C
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 2. Peak Output Current is applied for tp = 10 ms, duty cycle ≤1%

6.4 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance (top of package)(1) 22.8 °C/W
RθJB Junction-to-board thermal resistance(2) 2.5 °C/W
(1) RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch (1.52 mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power Loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C		 1.9 W
Power Loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C		 2.2 W
Power Loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 125°C		 2.6 W
VIN
IQ VIN quiescent current PWM = Floating, VDD = 5 V, VIN= 24 V 1 µA
VDD
IDD Standby supply current PWM = Float, SKIP# = VDD or 0 V 130 µA
SKIP# = Float 8 µA
IDD Operating supply current PWM = 50% Duty cycle, ƒSW = 500 kHz 7.8 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD Rising Power-on reset 4.15 V
VDD Falling UVLO 3.7 V
Hysteresis 0.2 mV
PWM AND SKIP# I/O SPECIFICATIONS
RI Input impedance Pull up to VDD 1700 kΩ
Pull down (to GND) 800
VIH Logic level high 2.65 V
VIL Logic level low 0.6
VIH Hysteresis 0.2
VTS Tri-state voltage 1.3 2
tTHOLD(off1) Tri-state activation time (falling) PWM(2) 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM(2) 60
tTSKF Tri-state activation time (falling) SKIP#(2) 1 µs
tTSKR Tri-state activation time (rising) SKIP# (2) 1
t3RD(PWM) Tri-state exit time PWM(2) 100 ns
t3RD(SKIP#) Tri-state exit time SKIP#(2) 50 µs
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK Reverse leakage(2) VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design.