SLASEX3 March   2021 DAC43204 , DAC53204 , DAC63204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Voltage Output
    6. 6.6  Electrical Characteristics - Current Output
    7. 6.7  Electrical Characteristics - Comparator Mode
    8. 6.8  Electrical Characteristics - General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation
    14. 6.14 Timing Requirements: GPIO
    15. 6.15 Timing Diagrams
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Application-Specific Modes
        1. 7.4.4.1 Voltage Margining and Scaling
          1. 7.4.4.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.4.1.2 Programmable Slew-Rate Control
          3. 7.4.4.1.3 PMBus Compatibility Mode
        2. 7.4.4.2 Function Generation
          1. 7.4.4.2.1 Triangular Waveform Generation
          2. 7.4.4.2.2 Sawtooth Waveform Generation
          3. 7.4.4.2.3 Sine Waveform Generation
      5. 7.4.5 Device Reset and Fault Management
        1. 7.4.5.1 Power-on-Reset (POR)
        2. 7.4.5.2 External Reset
        3. 7.4.5.3 Register-Map Lock
        4. 7.4.5.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.5.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.5.4.2 NVM-CRC-FAIL-INT Bit
      6. 7.4.6 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = TBD]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = D1h) [reset = 0000h]
      17. 7.6.17 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      18. 7.6.18 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      19. 7.6.19 PMBUS-PAGE Register (address = 51h) [reset = 0000h]
      20. 7.6.20 PMBUS-OP-CMD-X Register (address = 52h, 53h, 54h, 55h) [reset = 0000h]
      21. 7.6.21 PMBUS-CML Register (address = 56h) [reset = 0000h]
      22. 7.6.22 PMBUS-VERSION Register (address = 57h) [reset = 2200h]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.     Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Orderable Information

Features

  • Programmable voltage or current outputs with flexible configuration:
    • Voltage outputs:
      • 1 LSB INL and DNL (10-bit and 8-bit)
      • Gains of 1x, 1.5x, 2x, 3x, and 4x
    • Current outputs:
      • 1 LSB INL and DNL (8-bit)
      • ±25 μA, ±50 μA, ±125 μA, ±250 μA output range options
  • Programmable comparator mode for all channels
  • High-impedance output when VDD is off
  • High-impedance and resistive pulldown power-down modes
  • 25-MHz SPI-compatible interface
  • Automatically detected I2C, PMBus™, or SPI interface
    • 1.62-V VIH with VDD = 5.5 V
  • General-purpose input/output (GPIO) configurable as multiple functions
  • Predefined waveform generation: sine wave, triangular, sawtooth
  • User-programmable nonvolatile memory (NVM)
  • Internal, external, or power-supply as reference
  • Wide operating range:
    • Power supply: 1.8 V to 5.5 V
    • Temperature range: –40˚C to +125˚C
  • Tiny package: 16-pin WQFN (3 mm × 3 mm)