SLAS429E April   2005  – June 2017 DAC8551


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
      1. 6.7.1 VDD = 5 V
      2. 6.7.2 VDD = 2.7 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Section
        1. Resistor String
        2. Output Amplifier
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Input Shift Register
      3. 7.5.3 SYNC Interrupt
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using the DAC8551
    2. 8.2 Typical Application
      1. 8.2.1 Loop-Powered, 2-Wire, 4-mA to 20-mA Transmitter With XTR116
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 Using the REF02 as a Power Supply for the DAC8551
        1. Design Requirements
        2. Detailed Design Procedure
    3. 8.3 System Examples
      1. 8.3.1 Microprocessor Interfacing
        1. DAC8551 to 8051 Interface
        2. DAC8551 to Microwire Interface
        3. DAC8551 to 68HC11 Interface
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The low-power consumption of the DAC8551 lends itself to applications such as loop-powered control where the current dissipation of each device is critical. The low power consumption also allows the DAC8551 to be powered using only a precision reference for increased accuracy. The low-power operation coupled with the ultra-low power power-down modes also make the DAC8551 a great choice for battery and portable applications.

Bipolar Operation Using the DAC8551

The DAC8551 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 51. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the operational amplifier. See CMOS, Rail-to-Rail, I/O Operational Amplifiers (SBOS180) for more information.

DAC8551 ai_bipolar_las429.gif Figure 51. Bipolar Output Range

The output voltage for any input code can be calculated as follows:

Equation 2. DAC8551 q_vo1_las429.gif


  • D is the input code in decimal (0–65535)

With VREF = 5 V, R1 = R2 = 10 kΩ.

Equation 3. DAC8551 q_vo2_las429.gif

Using this example, an output voltage range of ±5 V—with 0000h corresponding to a –5-V output and FFFFh corresponding to a 5-V output—can be achieved. Similarly, using VREF = 2.5 V, a ±2.5-V output voltage range can be achieved.

Typical Application

Loop-Powered, 2-Wire, 4-mA to 20-mA Transmitter With XTR116

DAC8551 app-schem_SLASEB8.gif Figure 52. Loop-Powered Transmitter

Design Requirements

This design is commonly referred to as a loop-powered, or 2-wire, 4-mA to 20-mA transmitter. The transmitter has only two external input terminals: a supply connection and an output, or return, connection. The transmitter communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its return current. In order to conform to the 4-mA to 20-mA communication standard, the complete transmitter must consume less than 4 mA of current. The DAC8551 enables the accurate control of the loop current from 4 mA to 20 mA in 16-bit steps.

Detailed Design Procedure

Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides simplicity and improved performance due to the matched internal resistors. The output current can be modified if necessary by looking using Equation 4.

Equation 4. DAC8551 eq02-Iout_SLASEB8.gif

See 2-wire, 4-mA to 20-mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7) for more information. It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.

Application Curves

Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 53. The linearity of the output or INL is in Figure 54.

DAC8551 D001_SLASEB8.gif Figure 53. Total Unadjusted Error
DAC8551 D002_SLASEB8.gif Figure 54. Integral Nonlineareity

Using the REF02 as a Power Supply for the DAC8551

DAC8551 ai_ref02_ps_las429.gif Figure 55. REF02 as a Power Supply to the DAC8551

Design Requirements

Due to the extremely low supply current required by the DAC8551, an alternative option is to use the REF02 to supply the required voltage to the device, as illustrated in Figure 55. See +5V Precision Voltage Reference (SBVS003) for more inforation.

Detailed Design Procedure

This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC8551. If the REF02 is used, the current it needs to supply to the DAC8551 is 200 μA. This configuration is with no load on the output of the DAC. When a DAC output is loaded, the REF02 also needs to supply the current to the load.

The total typical current required (with a 5-kΩ load on the DAC output) is:

Equation 5. DAC8551 q4_250ua_las429.gif

The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2-mA current drawn from it. This value corresponds to a 3.9-LSB error.

System Examples

Microprocessor Interfacing

DAC8551 to 8051 Interface

Figure 56 shows a serial interface between the DAC8551 and a typical 8051-type microcontroller.

The interface is setup with the TXD of the 8051 drives SCLK of the DAC8551, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data are to be transmitted to the DAC8551, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DAC8551 requires data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and mirror the data as needed.

DAC8551 too_80c51_las429.gif Figure 56. DAC8551 to 80C51 or 80L51 Interface

DAC8551 to Microwire Interface

Figure 57 shows an interface between the DAC8551 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and is clocked into the DAC8551 on the rising edge of the SK signal.

DAC8551 too_micro_las429.gif Figure 57. DAC8551 to Microwire Interface

DAC8551 to 68HC11 Interface

Figure 58 shows a serial interface between the DAC8551 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8551, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.

DAC8551 too_68hc11_las429.gif Figure 58. DAC8551 to 68HC11 Interface

The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DAC8551, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation are performed to the DAC. PC7 is taken HIGH at the end of this procedure.