SLVSBY7 February   2017 DAC8775


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. Buck-Boost Converters Outputs
        2. Selecting and Enabling Buck-Boost Converters
        3. Configurable Clamp Feature and Current Output Settling Time
          1. Default Mode - CCLP[1:0] = "00" - Current Output Only
          2. Fixed Clamp Mode - CCLP[1:0] = "01" - Current and Voltage Output
          3. Auto Learn Mode - CCLP[1:0] = "10" - Current Output Only
          4. High Side Clamp (HSCLMP)
        4. Buck-Boost Converters and Open Circuit Current Output
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD Bits
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. Stand-Alone Operation
        2. Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. Asynchronous Mode
        2. Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 DAC8775 Commands
      2. 8.5.2 Register Maps and Bit Functions
        1.  No Operation Register (address = 0x00) [reset = 0x0000]
        2.  Reset Register (address = 0x01) [reset = 0x0000]
        3.  Reset Config Register (address = 0x02) [reset = 0x0000]
        4.  Select DAC Register (address = 0x03) [reset = 0x0000]
        5.  Configuration DAC Register (address = 0x04) [reset = 0x0000]
        6.  DAC Data Register (address = 0x05) [reset = 0x0000]
        7.  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
        8.  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
        9.  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
        10. DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
        11. DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
        12. Status Register (address = 0x0B) [reset = 0x1000]
        13. Status Mask Register (address = 0x0C) [reset = 0x0000]
        14. Alarm Action Register (address = 0x0D) [reset = 0x0000]
        15. User Alarm Code Register (address = 0x0E) [reset = 0x0000]
        16. Reserved Register (address = 0x0F) [reset = N/A]
        17. Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
        18. Device ID Register (address = 0x11) [reset = 0x0000]
        19. Reserved Register (address 0x12 - 0xFF) [reset = N/A]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Ouputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling time with Auto learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8775
    2. 9.2 Typical Application
      1. 9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Buck-Boost Converter External Component Selection

DAC8775 DCDC_Ext_Comp_slvsby7.gif Figure 127. DAC8775 External Buck-Boost Components with Recommended Values

The buck-boost converters integrated in the DAC8775 each require three external passive components for operation: a single inductor per channel as well as storage capacitors and switching diodes for each VPOS_IN_x and VNEG_IN_x channels that are active. If only one output is used, either VPOS_IN_x or VNEG_IN_x, the inactive output components may be removed and the respective inputs tied to ground. In order to meet the parametric performance outlined in the Electrical Characteristics section for the voltage output, 500 mV of foot-room is required on VNEG_IN_x.

The recommended value for the external inductor is 100 µH with at least 500 mA peak inductor current. Reducing the inductor value to as low as 80 µH is possible, though this will limit the buck-boost converter maximum input voltage to output voltage ratio, reduce efficiency, and increase ripple. Reducing the inductor below 80 µH will result in device damage. Peak inductor current should be rated at 500 mA or greater with 20% inductance tolerance at peak current. If peak inductor current for an inductor is violated the effective inductance is reduced, which will impact maximum input to output voltage ratio, efficiency, and ripple.

An output, or storage, X7R capacitor with value of 10 µF and voltage rating of 50 V is recommended though other values and dielectric materials may be used without damaging the DAC8775. Reducing capacitor value will increase buck-boost converter output ripple and reduced voltage rating will reduce effective capacitance at full-scale buck-boost converter outputs. X7R capacitors are rated for –55°C to 125°C operation with 15% maximum capacitance variance over temperature. Designs operating over reduced temperature spans and with loose efficiency requirements may use different dielectric material. C0G capacitor typically offer tighter capacitance variance but come in larger packages, but may be beneficial substitutes.

The external diode switches illustrated on the left and right side of the 100 µH inductor shown in Figure 127 should be selected based on reverse voltage rating, reverse recovery time, leakage or parasitic capacitance, and current or power ratings. Breakdown voltage rating of at least 60 V is recommended to accommodate for the maximum voltage that may be across the diode when both VPOS_x and VNEG_x are both active during switching of the DC/DCs. Minimal reverse recovery time and parasitic capacitance is recommended in order to preserve efficiency of the DC/DCs. The external diode should be rated for at least 500 mA average forward current.

Voltage and Current Ouputs on a Shared Terminal

Figure 128 illustrates a simplified block diagram of the voltage output stages of the DAC8775.

DAC8775 VOUT_Arch_slvsby7.gif Figure 128. Simplified Block Diagram of Voltage Output Architecture

When designing for a shared voltage and current output terminal it is important to consider leakage paths that may corrupt the voltage or current output stages.

When the voltage output is active and the current output is inactive the IOUT_x pin becomes a high-impedance node and therefore does not significantly load the voltage output in a way that would degrade VOUT_x performance. When the voltage output is inactive and the current output is active switches S1, S2, and S4 all become open while switch S3 is controlled by the POC bit in the Reset Config Register for each respective channel. When the POC bit is set to a 0, the default value, switch S3 is closed when VOUT is disabled. This creates a leakage path with respect to the current output when the terminals are shared which will create a load-dependent error. In order to reduce this error the POC bit can be set to a 1 which opens switch S3, effectively making the VOUT pin high-impedance and reducing the magnitude of leakage current.

Optimizing Current Output Settling time with Auto learn Mode

When the buck-boost converters are active power and heat dissipation of the device are at a minimum, however settling time of the current output is dominated by the slew rate of the buck-boost converter, which is significantly slower that the current output signal chain alone. When the buck-boost converters are bypassed settling time of the current output is minimized while power and heat dissipation are significant.

Auto-learn mode offers an alternative mode which allows the buck-boost converter to learn the size of the load and choose a clamped output value that does not change over the full range of the selected current output. This allows a balance between settling time and power dissipation. There are two options for entering auto-learn mode:

  • Enable the buck-boost converter in full-tracking mode followed by enabling the current output. Until the DAC code 0x4000 is passed, settling time will be dominated by the buck-boost converter. After code 0x400 is surpassed the buck-boost converter detects the load and sets the clamp value appropriately.
  • Enable the buck-boost converter in clamp-mode with clamp value set to a greater voltage than required by the largest load the current output will be expected to drive, followed by enabling the current output. Enter full-tracking mode. In this case the clamp value of maintained without the buck-boost converter output changing, therefore settling time is set by the IOUT_x signal chain. After code 0x4000 is surpassed the buck-boost converter detects the load and adjusts the clamp value appropriately. At all times using this initialization procedure the settling time is defined by the IOUT_x signal chain.

Protection for Industrial Transients

In order to successfully protect the DAC8775, or any integrated circuit, against industrial transient testing the internal structures and how they may behave when exposed to said signals must be understood. Figure 129 depicts a simplified representation of internal structures present on the device’s output pins which are represented as a pair of clamp-to-rail diodes connected to the VPOS_IN_x and VNEG_IN_x supply rails.

DAC8775 Pro_Cir_slvsby7.gif Figure 129. Simplified Block Diagram of Internal Structures and External Protection

When these internal structures are exposed to industrial transient testing, without the external protection components, the diode structures will become forward biased and conduct current. If the conducted current is too large, which is often true for high-voltage industrial transient tests, the structures will become permanently damaged and impact device functionality.

Both attenuation and diversion strategies are implemented to protect the internal structures as well as the device itself. Attenuation is realized by capacitor C4 which forms an R/C low-pass filter when interacting with the source impedance of the transient generator, ferrite bead FB1 also helps attenuate high-frequency current, along with both AC and DC current limiters realized by series pass elements R1, R2, and R3. Diversion is achieved by transient voltage suppressor (TVS) diode D7 and clamp-to-rail diodes D5 and D6. The combined effects of both strategies effectively limit the current flowing into the device and through the internal diode structures such that the device is not damaged and remains functional.

It is important to also include TVS diodes D1 and D4 at the VPOS_IN_x and VNEG_IN_x nodes in order to provide a discharge path for the energy that is going to be sent to these nodes through diodes D5, D6, and the internal diode structures. Without these diodes when current is diverted to these nodes the DC/DC converter storage capacitors C1 and C2 will charge, slowly increasing the voltage at these nodes.

Implementing HART with DAC8775

The DAC8775 features internal resistors to convert a 500-mVpp HART FSK signal sourced by an external HART modem. These resistors are ratiometrically matched to the gain-setting resistors for the current output signal chain to ensure that a 500-mVpp input at the HART_IN_x pin is delivered as a 1-mApp signal at the respective IOUT_x pin regardless of which gain mode is selected.

An external capacitor, placed in series between the HART_IN_x pin and HART FSK source, is required to AC couple the HART FSK signal to the HART_IN_x pin. The recommended capacitance for this external capacitor is from 10 nF to 22 nF.

Typical Application

1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management

DAC8775 Typ_App_slvsby7.gif Figure 130. DAC8775 in Quad-Channel PLC AO Module

Design Requirements

Analog I/O modules are used by programmable logic controllers (PLCs) to interface sensors, actuators, and other field instruments. These modules must meet stringent electrical specifications for both accuracy and robust protection. These outputs are typically current outputs based on the 4-mA to 20-mA range and derivatives or voltage outputs ranging from 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V. Common error budgets accommodate 0.1% full-scale range total unadjusted error (% FSR TUE) at room temperature. Designs that desire stronger accuracy over temperature frequently implement calibration. Often the PLC back-plane provides access to a 12-V to 36-V analog supply from which a majority of analog supply voltages are derived.

Analog output modules are frequently multi-channel modules featuring either channel-to-channel isolation between each channel or group isolation where several channels share a common ground connection. As channel count increases it is desirable to maintain small form-factor requiring high levels of integration and reduced power dissipation in order to control heat inside of the PLC enclosure.

Therefore the design requirements are:

  • Support of standard industrial automation voltage and current output spans
  • Operation with standard industrial automation supply voltages from 12 V to 36 V
  • Current and voltage outputs with TUE less than 0.1% at 25°C
  • Total on-board power dissipation less than or equal to 1 W
  • At minimum criteria B IEC61000-4 ESD, EFT, CI, and Surge immunity

Detailed Design Procedure

DAC8775 Gen_AO_Mod_slvsby7.gif Figure 131. Generic Design for Typical PLC Current and Voltage Outputs

Figure 131 illustrates a common generic solution for realizing the desired voltage and current output spans for industrial automation applications.

The current output circuit is comprised of amplifiers A1 and A2, MOSFETs Q1 and Q2, and the three resistors RSET, RA, and RB. This two-stage current source enables the ground-referenced DAC output voltage to drive the high-side amplifier required for the current-source.

The voltage output circuit is composed of amplifier A3 and the resistor network consisting of RFB, RG1, and RG2. A3 operates as a modified summing amplifier, where the DAC controls the non-inverting input and inverting input has one path to GND and a second to VREF. This configuration allows the single-ended DAC to create both the unipolar 0-V to 5-V and 0-V to 10-V outputs and the bipolar ±5-V and ±10-V outputs by modifying the values of RG1 and RG2.

Though this generic circuit realizes the desired spans, both the voltage and current outputs have short-comings. The current output high-side supply voltage is typically 24 V, when driving low impedance loads with this supply voltage a considerable amount of power is dissipated on RB and Q2. This power dissipation results in increased heat which leads to drift errors for amplifiers A1 and A2 as well as the DAC, resistors, and the reference voltage. In order to reduce the power dissipation in the high-side voltage to current converter circuit a feedback system which monitors the voltage drop across Q2 and adaptively adjusts the high-side supply voltage can be implemented. This feedback system adjusts the high side supply voltage to the minimum supply required to keep Q2 in the linear region of operation, avoiding compliance voltage saturation, reducing power dissipation and heat to a minimum which helps maintain accuracy.

The generic voltage output circuit performs well but does not compensate for errors associated with excessive output impedance or differences in ground potential from the local PLC ground and the load ground. A modified circuit can be implemented which provides connections to sense errors associated with both output impedance voltage drops and differences in ground potentials, this circuit is shown in Figure 128.

Figure 130 illustrates the DAC8775 along with the LM5166 in a quad-channel PLC analog output module. The DAC8775 includes the generic voltage and current output circuits along with buck-boost converter and feedback circuits for the current output and positive and negative sense connections for the voltage output circuit. The DAC8775 includes an internal reference and internal LDO for supplying the field-side of a digital isolator along with the buck-boost converter generating the single or dual high voltage supplies required for the output circuits, all powered from a single supply.

The DAC8775 buck-boost converter operates at peak efficiency with 12-V input voltage with peak power consumption of approximately 780mW. The LM5166 circuit accepts a wide range of input voltages from just above 12 V to 65 V, providing coverage for most standard PLC supply voltages, and buck-converts this supply voltage to the optimal 12-V supply for the DAC8775. Cumulative power dissipation for the DAC8775 and LM5166 is under 1 W.

Two ISO7641 devices implement galvanic isolation for all of the digital communication lines, though only a single ISO7641 is required for basic communication with the DAC8775 SPI compatible interface. An output protection circuit is included which is designed to provide immunity to the IEC61000-4 industrial transient and radiation test suite. The protection circuit includes transient voltage suppressor (TVS) diodes, clamp-to-rail steering diodes, and pass elements in the form of resistors and ferrite beads.

Application Curves

DAC8775 T001_IOUT_TUE.png Figure 132. 4-mA to 20-mA IOUT TUE vs Code
DAC8775 T003_PDiss.png Figure 134. Total On-Board Power Dissipation vs Supply
DAC8775 T002_VOUT_TUE.png Figure 133. ±10-V VOUT TUE vs Code