SLVSBY7 February   2017 DAC8775


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. Buck-Boost Converters Outputs
        2. Selecting and Enabling Buck-Boost Converters
        3. Configurable Clamp Feature and Current Output Settling Time
          1. Default Mode - CCLP[1:0] = "00" - Current Output Only
          2. Fixed Clamp Mode - CCLP[1:0] = "01" - Current and Voltage Output
          3. Auto Learn Mode - CCLP[1:0] = "10" - Current Output Only
          4. High Side Clamp (HSCLMP)
        4. Buck-Boost Converters and Open Circuit Current Output
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD Bits
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. Stand-Alone Operation
        2. Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. Asynchronous Mode
        2. Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 DAC8775 Commands
      2. 8.5.2 Register Maps and Bit Functions
        1.  No Operation Register (address = 0x00) [reset = 0x0000]
        2.  Reset Register (address = 0x01) [reset = 0x0000]
        3.  Reset Config Register (address = 0x02) [reset = 0x0000]
        4.  Select DAC Register (address = 0x03) [reset = 0x0000]
        5.  Configuration DAC Register (address = 0x04) [reset = 0x0000]
        6.  DAC Data Register (address = 0x05) [reset = 0x0000]
        7.  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
        8.  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
        9.  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
        10. DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
        11. DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
        12. Status Register (address = 0x0B) [reset = 0x1000]
        13. Status Mask Register (address = 0x0C) [reset = 0x0000]
        14. Alarm Action Register (address = 0x0D) [reset = 0x0000]
        15. User Alarm Code Register (address = 0x0E) [reset = 0x0000]
        16. Reserved Register (address = 0x0F) [reset = N/A]
        17. Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
        18. Device ID Register (address = 0x11) [reset = 0x0000]
        19. Reserved Register (address 0x12 - 0xFF) [reset = N/A]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Ouputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling time with Auto learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8775
    2. 9.2 Typical Application
      1. 9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

An example layout based on the design discussed in the Typical Application section is shown in the Layout Example section. Figure 139 shows the top-layer of the design which illustrates all component placement as no components are placed on the bottom layer. Figure 140 shows two of the internal power-layers: the layer on the left contains VPOS_IN_B, VPOS_IN_C, VNEG_IN_B, and VNEG_IN_D nets while the layer on the right contains VPOS_IN_A, VPOS_IN_D, VNEG_IN_A, and VNEG_IN_C nets.

The layer stack-up for this 6-layer example layout is shown below. A 6-layer design is not required, however provides optimal conditions for ground and power-supply planes. The solid ground plane beneath the majority of the signal traces, which are placed on the top layer, allows for a clean return path for sensitive analog traces and keeps them isolated from the internal power supply nets which will exhibit ripple from the DC/DC converter.

DAC8775 Lyr_Stack2_slvsby7.gif Figure 138. Example Layout Layer Stack-Up

Traces for the DC/DC external components should be as low impedance, low inductance, and low capacitance as possible in order to maintain optimum performance. As such wide traces should be used to minimize inductance with minimal use of vias as vias will contribute large inductance and capacitance to the trace. For this reason it is recommended that all DC/DC components placed on the top layer.

The industrial transient protection circuit should be placed as close to the output connectors as possible to ensure that the return currents from these transients have a controlled path to exit the PCB which does not impact the analog circuitry.

Split ground planes for the DC/DC, digital, and analog grounds are not required but may be helpful to isolated ground return currents from cross-talk. If split ground planes are used care should be taken to ensure that signal traces are only placed above or below the locations where their respective grounds are placed in order to mitigate unexpected return paths or coupling to the other ground planes. If a single ground plane is used it is advisable to follow similar practices implementing a star-ground where the respective return currents interact with one another minimally. The example layout uses a single ground plane, based on measured results, performs similarly to an identical version with split ground planes.

The perimeter of the board is stitched with vias in order to enhance design performance against environments which may include radiated emissions. Additional vias are placed in critical areas nearby the design in order to place ground pours in between nodes to reduce cross-talk between adjacent traces.

Standard best-practices should be applied to the remaining components, including but not limited to, placing decoupling capacitors close to their respective pins and using wide traces or copper pours where possible, particularly for power traces where high current may flow.

Layout Example

DAC8775 PCB_Top_Lyr_slvsby7.gif Figure 139. Application Example Layout
DAC8775 PCB_Pwr_Lyrs_slvsby7.gif Figure 140. Example Design Internal Copper Pours