DLPS099B February   2018  – May 2022 DLP3010

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-41F81BC8-8FAD-4F8C-954F-EF37F00B92C8-low.gif Figure 5-1 FQK Package. 57-Pin LGA. BOTTOM VIEW.
Table 5-1 Pin Functions – Connector Pins
PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_N(0) C9 I SubLVDS Double Data, Negative 10.54
D_P(0) B9 I SubLVDS Double Data, Positive 10.54
D_N(1) D10 I SubLVDS Double Data, Negative 13.14
D_P(1) D11 I SubLVDS Double Data, Positive 13.14
D_N(2) C11 I SubLVDS Double Data, Negative 14.24
D_P(2) B11 I SubLVDS Double Data, Positive 14.24
D_N(3) D12 I SubLVDS Double Data, Negative 14.35
D_P(3) D13 I SubLVDS Double Data, Positive 14.35
D_N(4) D4 I SubLVDS Double Data, Negative 5.89
D_P(4) D5 I SubLVDS Double Data, Positive 5.89
D_N(5) C5 I SubLVDS Double Data, Negative 5.45
D_P(5) B5 I SubLVDS Double Data, Positive 5.45
D_N(6) D6 I SubLVDS Double Data, Negative 8.59
D_P(6) D7 I SubLVDS Double Data, Positive 8.59
D_N(7) C7 I SubLVDS Double Data, Negative 7.69
D_P(7) B7 I SubLVDS Double Data, Positive 7.69
DCLK_N D8 I SubLVDS Double Clock, Negative 8.10
DCLK_P D9 I SubLVDS Double Clock, Positive 8.10
CONTROL INPUTS
LS_WDATA C12 I LPSDR(1) Single Write data for low-speed interface. 7.16
LS_CLK C13 I LPSDR Single Clock for low-speed interface. 7.89
DMD_DEN_ARSTZ C14 I LPSDR Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode.
LS_RDATA C15 O LPSDR Single Read data for low-speed interface.
POWER
VBIAS(3) C1 Power Supply voltage for positive bias level at micromirrors.
VBIAS(3) C18 Power
VOFFSET(3) D1 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors.
VOFFSET(3) D17 Power
VRESET B1 Power Supply voltage for negative reset level at micromirrors.
VRESET B18 Power
VDD B6 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes.
VDD B10 Power
VDD B19 Power
VDD(3) C6 Power
VDD C10 Power
VDD C19 Power
VDD D2 Power
VDD D18 Power
VDD D19 Power
VDDI B2 Power Supply voltage for SubLVDS receivers.
VDDI C2 Power
VDDI C3 Power
VDDI D3 Power
VSS B3 Ground Common return.
Ground for all power.
VSS B4 Ground
VSS B8 Ground
VSS B12 Ground
VSS B13 Ground
VSS B14 Ground
VSS B15 Ground
VSS B16 Ground
VSS B17 Ground
VSS C4 Ground
VSS C8 Ground
VSS C16 Ground
VSS C17 Ground
VSS D14 Ground
VSS D15 Ground
VSS D16 Ground
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Net trace lengths inside the package:
Relative dielectric constant for the FQK ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/in = 265 ps/in = 10.43 ps/mm.
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
Table 5-2 Pin Functions – Test Pads
NUMBER SYSTEM BOARD
A13 Do not connect
A14 Do not connect
A15 Do not connect
A16 Do not connect
A17 Do not connect
A18 Do not connect
E13 Do not connect
E14 Do not connect
E15 Do not connect
E16 Do not connect
E17 Do not connect
E18 Do not connect