DLPS284 December   2025 DLP3940S-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12.     18
    13. 5.10 Micromirror Array Physical Characteristics
    14.     20
    15. 5.11 Micromirror Array Optical Characteristics
    16. 5.12 Window Characteristics
    17. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 Power Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
      5. 7.2.5 Design Requirements
      6. 7.2.6 Detailed Design Procedure
    3. 7.3 Temperature Sensing
      1. 7.3.1 Temperature Sensing Diode
        1. 7.3.1.1 Temperature Sense Diode Theory
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
    3. 8.3 DMD Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • FSC|154
Thermal pad, mechanical data (Package|Pins)

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted).
MIN TYP MAX UNIT
SUPPLY VOLTAGE RANGE
VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface (1)(2) 1.71 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers (1)(2) 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (1)(2)(3) 9.5 10 10.5 V
VBIAS Supply voltage for mirror electrode (1)(2) 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode (1)(2) –14.5 –14 –13.5 V
| VDDI - VDD | Supply voltage delta (absolute value) (1)(2)(4) 0.3 V
| VBIAS-VOFFSET | Supply voltage delta (absolute value) (1)(2)(5) 10.5 V
| VBIAS - VRESET | Supply voltage delta (absolute value) (1)(2)(6) 33 V
LPSDR INTERFACE
VIH High-level input voltage 0.7 x VDD V
VIL Low-level input voltage 0.3 x VDD V
VIH(AC) AC input high voltage 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage –0.3 0.2 × VDD V
VHyst Input Hysteresis 0.1 × VDD 0.4 × VDD V
fmax_LS Clock frequency for low speed interface LS_CLK (7) 108 120 130 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) (7) 44 56 %
SUBLVDS INTERFACE
fmax_HS Clock frequency for high-speed interface DCLK (8) 600 720 MHz
DCDIN LVDS duty cycle distortion (DCLK) 48 52 %
| VID | LVDS differential input voltage magnitude (8) 150 250 350 mV
VCM Common mode voltage (8) 700 900 1100 mV
VSUBLVDS SubLVDS voltage (8) 525 1275 mV
ZIN Internal differential termination resistance 80 100 120 Ω
TEMPERATURE DIODE
ITEMP_DIODE Max current source into Temperature Diode 120 µA
ENVIRONMENTAL
TARRAY Array temperature, long-term operation (9)(10)(11) -40 105 °C
QAP-ILL Window aperture illumination overfill (12)(13)(14) 80 mW/mm2
ILLUMINATION
ILLUV Illumination power at wavelengths < 410 nm (9)(15) 10 mW/cm2
(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) All voltage values are concerning the ground pins (VSS).
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(7) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(8) Refer to the SubLVDS timing requirements in Timing Requirements.
(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces the device's lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at the test point (TP1) shown in Figure 6-5 and the package thermal resistance using the Micromirror Array Temperature Calculation.
(11) Long-term is defined as the usable life of the device.
(12) Applies to region defined in Figure 5-1.
(13) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly for normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system the amount of overfill light on the outside of the active array may cause system performance degradation.