DLPS101B Data sheet

6.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted).

		MIN	NOM	MAX	UNIT
LVDS#T4989946-35
t_c	Clock Cycle for DLCK_A	3.03			ns
t_c	Clock Cycle for DCLKC_B	3.03			ns
t_w	Pulse Duration DCLK_A	1.36	1.52		ns
t_w	Pulse Duration for DCLK_B	1.36	1.52		ns
t_SU	Setup Time, D_A[0:15] before DCLK_A	0.35			ns
t_SU	Setup Time, D_B[0:15] before DCLK_B	0.35			ns
t_SU	Setup Time, SCTRL_A before DCLK_A	0.35			ns
t_SU	Setup Time, SCTRL_B before DCLK_B	0.35			ns
t_H	Hold Time, D_A[0:15] after DCLK_A	0.35			ns
t_H	Hold Time, D_B[0:15] after DCLK_B	0.35			ns
t_H	Hold Time, SCTRL_A after DCLK_A	0.35			ns
t_H	Hold Time, SCTRL_B after DCLK_B	0.35			ns
t_skew	Channel B relative to Channel A#T4989946-36 #T4989946-37	–1.51		1.51	ns

(1) See #DLPS0952F2 for timing requirements for LVDS.

(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).

(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).

Figure 6-2 SCP Timing Parameters

Not to scale

Refer to #GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.

Refer to GUID-B0CCC92B-1768-4A99-BB7C-8E88C03ABC21.html#GUID-B0CCC92B-1768-4A99-BB7C-8E88C03ABC21 for list of LVDS pins and SCP pins.

Figure 6-3 Rise Time and Fall Time

Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System design should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See #T4989946-26.