DLPS249 December   2024 DLP991U

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Power-Up Procedure
      2. 7.4.2 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 PCB Design Standards
        2. 7.5.1.2 General PCB Routing
          1. 7.5.1.2.1 Trace Impedance and Routing Priority
          2. 7.5.1.2.2 Example PCB Layer Stack-Up
          3. 7.5.1.2.3 Trace Width, Spacing
          4. 7.5.1.2.4 Power and Ground Planes
          5. 7.5.1.2.5 Trace Length Matching
            1. 7.5.1.2.5.1 HSSI Input Bus Skew
            2. 7.5.1.2.5.2 Other Timing Critical Signals
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 DMD Power Supply Power-Down Procedure

  • During power-down, VDD and VDDA must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. See Table 7-3.
  • During power-down, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be within the specified limit shown in Section 5.4.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 5.1, in Section 5.4, and in Figure 7-3.
  • During power-down, LVCMOS input pins must be less than specified in Section 5.4.
DLP991U DMD Power Supply RequirementsFigure 7-3 DMD Power Supply Requirements
  1. See Section 4.
  2. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 5.4.
  3. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit in Section 5.4.
  4. VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in Table 7-3.
  5. DLP controller software initiates the global VBIAS command.
  6. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates DMD_EN_ARSTZ and disables VBIAS, VRESET, and VOFFSET.
  7. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware DMD_EN_ARSTZ will go low.
  8. VDD / VDDA must remain above the minimum values specified in Section 6.4 until after VOFFSET, VBIAS, VRESET go low, per Delay2 specification in Table 7-3.
  9. To prevent excess current, the supply voltage delta |VDDA – VDD| must be less than specified limit in Section 5.4.
Table 7-3 DMD Power-Supply Requirements
PARAMETER DESCRIPTION MIN NOM MAX UNIT
Delay1 Delay from VOFFSET settled at recommended operating voltage to VBIAS and VRESET power up. 1 2 ms
Delay2 Delay VDD must be held high from VOFFSET, VBIAS and VRESET powering down. 50 μs
Delay3 Delay from VBIAS and VRESET settled at recommended operating voltage to DMD_EN_ARSTZ being asserted. 20 μs