DLPS015F April   2010  – November 2022 DLPA200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Configurations Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics Control Logic
    6. 7.6  5-V Linear Regulator
    7. 7.7  Bias Voltage Boost Converter
    8. 7.8  Reset Voltage Buck-Boost Converter
    9. 7.9  VOFFSET/DMDVCC2 Regulator
    10. 7.10 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Linear Regulator
      2. 8.3.2 Bias Voltage Boost Converter
      3. 8.3.3 Reset Voltage Buck-Boost Converter
      4. 8.3.4 VOFFSET/DMDVCC2 Regulator
      5. 8.3.5 Serial Communications Port (SCP)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Component Selection Guidelines
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Rail Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding Guidelines
    2. 11.2 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Generates the micromirror clocking pulses required by the DLP® Digital Micromirror Device (DMD)
  • Generates specialized voltage levels required for micromirror clocking pulse generation
  • Designed for use in multiple DLP chipsets