SNOSAY8 Data sheet

SNOSAY8F September 2007 – April 2015 DP83640

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PT|48
- MTQF003C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Supply Voltage (V_CC)	–0.5	4.2	V
DC Input Voltage (V_IN)		–0.5 to V_CC + 0.5	V
DC Output Voltage (V_OUT)		–0.5 to V_CC + 0.5	V
Maximum Case Temperature for T_A = 85 °C		95	°C
Maximum Die Temperature (T_J)		150	°C
Lead Temperature (T_L) (Soldering, 10 s)		260	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽³⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±8000	V
V_(ESD)	Electrostatic discharge⁽³⁾	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) R_ZAP = 1.5k, C_ZAP = 120 pF

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Analog Supply Voltage (V_CC)		3.3 ± 0.3	V
I/O Supply Voltage (V_I/O)		3.3 ± 10% or 2.5 ± 5%	V
Industrial Temperature (T_I)	–40	85	°C
Power Dissipation (P_D) with V_I/O = 3.3 V		290	mW
Power Dissipation (P_D) with V_I/O = 2.5 V		260	mW

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		PT	UNIT
THERMAL METRIC⁽¹⁾		48 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	53.3⁽²⁾	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.7	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) No Airflow @ 1 W.

4.5 DC Specifications

	PIN TYPES	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	I I/O	Input High Voltage		2.0			V
V_IL	I I/O	Input Low Voltage	V_I/O = 3.3 V			0.8	V
V_IL	I I/O	Input Low Voltage	V_I/O = 2.5 V			0.7	V
I_IH	I I/O	Input High Current	V_IN = V_I/O			10	µA
I_IL	I I/O	Input Low Current	V_IN = GND			10	µA
V_OL	O I/O	Output Low Voltage	I_OL = 4 mA			0.4	V
V_OH	O I/O	Output High Voltage	I_OH = -4 mA	V_I/O - 0.5			V
I_OZ	O I/O	TRI-STATE Output Leakage Current	V_OUT = V_I/O or GND	–10		10	µA
V_{TPTD_100}	PMD Output Pair	100M Transmit Voltage		0.95	1	1.05	V
V_TPTDsym	PMD Output Pair	100M Transmit Voltage Symmetry				±2%
V_{TPTD_10}	PMD Output Pair	10M Transmit Voltage		2.2	2.5	2.8	V
V_{FXTD_100}	PMD Output Pair	FX 100M Transmit Voltage		0.3	0.5	0.93	V
C_IN1	I	CMOS Input Capacitance			8		pF
C_OUT1	O	CMOS Output Capacitance			8		pF
S_DTHon	PMD Input Pair	100BASE-TX Signal detect turnon threshold				1000	mV diff pk-pk
S_DTHoff	PMD Input Pair	Signal detect turnoff threshold		200			mV diff pk-pk
V_TH	PMD Input Pair	10BASE-T Receive Threshold		300		585	mV
I_dd100	Supply	100BASE-TX (Full Duplex)	V_CC = 3.3 V, V_I/O = 3.3 V, I_OUT = 0 mA⁽¹⁾		88		mA
I_dd100	Supply	100BASE-TX (Full Duplex)	V_CC = 3.3 V, V_I/O = 2.5 V, I_OUT = 0 mA⁽¹⁾		84		mA
I_dd10	Supply	10BASE-T (Full Duplex)	V_CC = 3.3 V, V_I/O = 3.3 V, I_OUT = 0 mA⁽¹⁾		105		mA
I_dd10	Supply	10BASE-T (Full Duplex)	V_CC = 3.3 V, V_I/O = 2.5 V, I_OUT = 0 mA⁽¹⁾		103		mA
I_dd	Supply	Power Down Mode	CLK_OUT disabled		10		mA

(1) For I_dd measurements, outputs are not loaded

4.6 AC Timing Requirements

PARAMETER	DESCRIPTION	NOTES	MIN	TYP	MAX	UNIT
POWER-UP TIMING (Refer to Figure 4-1)
T2.1.1	Post Power Up Stabilization time prior to MDC preamble for register accesses⁽¹⁾	MDIO is pulled high for 32-bit serial management initialization.	167			ms
T2.1.2	Hardware Configuration Latch-in Time from power up⁽¹⁾	Hardware Configuration Pins are described in Section 3.	167			ms
T2.1.3	Hardware Configuration pins transition to output drivers			50		ns
RESET TIMING (Refer to Figure 4-2)
T2.2.1	Post RESET Stabilization time prior to MDC preamble for register accesses	MDIO is pulled high for 32-bit serial management initialization		3		µs
T2.2.2	Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)	Hardware Configuration Pins are described in Section 3		3		µs
T2.2.3	Hardware Configuration pins transition to output drivers⁽²⁾			50		ns
T2.2.4	RESET pulse width	X1 Clock must be stable for at min. of 1 µs during RESET pulse low time.	1			µs
MII SERIAL MANAGEMENT TIMING (Refer to Figure 4-3)
T2.3.1	MDC to MDIO (Output) Delay Time		0		20	ns
T2.3.2	MDIO (Input) to MDC Setup Time		10
T2.3.3	MDIO (Input) to MDC Hold Time		10
T2.3.4	MDC Frequency			2.5	25	MHz
100 Mb/s MII TRANSMIT TIMING (Refer to Figure 4-4)
T2.4.1	TX_CLK High/Low Time	100 Mb/s Normal mode	16	20	24	ns
T2.4.2	TXD[3:0], TX_EN Data Setup to TX_CLK		10
T2.4.3	TXD[3:0], TX_EN Data Hold from TX_CLK		0
100 Mb/s MII RECEIVE TIMING (Refer to Figure 4-5)
T2.5.1	RX_CLK High/Low Time⁽³⁾	100 Mb/s Normal mode	16	20	24	ns
T2.5.2	RX_CLK to RXD[3:0], RX_DV, RX_ER Delay	100 Mb/s Normal mode	10		30	ns
100BASE-TX AND 100BASE-FX MII TRANSMIT PACKET LATENCY TIMING (Refer to Figure 4-6)
T2.6.1	TX_CLK to PMD Output Pair Latency⁽⁵⁾	100BASE-TX and 100BASE-FX modes IEEE 1588 One-Step Operation enabled⁽⁴⁾		5 9		bits
100BASE-TX AND 100BASE-FX MII TRANSMIT PACKET DEASSERTION TIMING (Refer to Figure 4-7)
T2.7.1	TX_CLK to PMD Output Pair Deassertion⁽⁶⁾	100BASE-TX and 100BASE-FX modes		5		bits
100BASE-TX TRANSMIT TIMING (t_R/F and Jitter) (Refer to Figure 4-8)
T2.8.1	100 Mb/s PMD Output Pair t_R and t_F⁽⁸⁾		3	4	5	ns
T2.8.1	100 Mb/s t_R and t_F Mismatch⁽⁷⁾				500	ps
T2.8.2	100 Mb/s PMD Output Pair Transmit Jitter				1.4	ns
100BASE-TX AND 100BASE-FX MII RECEIVE PACKET LATENCY TIMING (Refer to Figure 4-9)
T2.9.1	Carrier Sense ON Delay⁽⁹⁾	100BASE-TX mode		20		bits⁽¹⁰⁾
T2.9.1	Carrier Sense ON Delay⁽⁹⁾	100BASE-FX mode		10
T2.9.2	Receive Data Latency⁽¹¹⁾⁽¹²⁾	100BASE-TX mode		24
T2.9.2	Receive Data Latency⁽¹¹⁾⁽¹²⁾	100BASE-FX mode		14
100BASE-TX AND 100BASE-FX MII RECEIVE PACKET DEASSERTION TIMING (Refer to Figure 4-10)
T2.10.1	Carrier Sense OFF Delay⁽¹³⁾	100BASE-TX mode		24		bits⁽¹⁴⁾
T2.10.1	Carrier Sense OFF Delay⁽¹³⁾	100BASE-FX mode		14		bits⁽¹⁴⁾
10 Mb/s MII TRANSMIT TIMING⁽¹⁵⁾ (Refer to Figure 4-11)
T2.11.1	TX_CLK High/Low Time	10 Mb/s MII mode	190	200	210	ns
T2.11.2	TXD[3:0], TX_EN Data Setup to TX_CLK falling edge	10 Mb/s MII mode	25
T2.11.3	TXD[3:0], TX_EN Data Hold from TX_CLK rising edge	10 Mb/s MII mode	0
10 Mb/s MII RECEIVE TIMING (Refer to Figure 4-12)
T2.12.1	RX_CLK High/Low Time⁽¹⁶⁾		160	200	240	ns
T2.12.2	RXD[3:0], RX_DV transition delay from RX_CLK rising edge	10 Mb/s MII mode	100
T2.12.3	RX_CLK rising edge delay from RXD[3:0], RX_DV valid data	10 Mb/s MII mode	100
10BASE-T MII TRANSMIT TIMING (START OF PACKET) (Refer to Figure 4-13)
T2.13.1	Transmit Output Delay from the	10 Mb/s MII mode		3.5		bits⁽¹⁷⁾
T2.13.1	Falling Edge of TX_CLK	10 Mb/s MII mode		3.5		bits⁽¹⁷⁾
10BASE-T MII TRANSMIT TIMING (END OF PACKET) (Refer to Figure 4-14)
T2.14.1	End of Packet High Time		250	300		ns
T2.14.1	(with '0' ending bit)		250	300		ns
T2.14.2	End of Packet High Time		250	300		ns
T2.14.2	(with '1' ending bit)		250	300		ns
10BASE-T MII RECEIVE TIMING (START OF PACKET) (Refer to Figure 4-15)
T2.15.1	Carrier Sense Turnon Delay (PMD Input Pair to CRS)			630	1000	ns
T2.15.2	RX_DV Latency⁽¹⁸⁾			10		bits⁽¹⁹⁾
T2.15.3	Receive Data Latency	Measurement shown from SFD		8		bits⁽¹⁹⁾
10BASE-T MII RECEIVE TIMING (END OF PACKET) (Refer to Figure 4-16)
T2.16.1	Carrier Sense Turnoff Delay				1.0	µs
10 Mb/s HEARTBEAT TIMING (Refer to Figure 4-17)
T2.17.1	CD Heartbeat Delay	All 10 Mb/s modes		1200		ns
T2.17.2	CD Heartbeat Duration	All 10 Mb/s modes		1000		ns
10 Mb/s JABBER TIMING (Refer to Figure 4-18)
T2.18.1	Jabber Activation Time			85		ms
T2.18.2	Jabber Deactivation Time			500		ms
10BASE-T NORMAL LINK PULSE TIMING⁽²⁰⁾ (Refer to Figure 4-19)
T2.19.1	Pulse Width			100		ns
T2.19.2	Pulse Period			16		ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING⁽²¹⁾ (Refer to Figure 4-20)
T2.20.1	Clock, Data Pulse Width			100		ns
T2.20.2	Clock Pulse to Clock Pulse Period			125		µs
T2.20.3	Clock Pulse to Data Pulse Period	Data = 1		62		µs
T2.20.4	Burst Width			2		ms
T2.20.5	FLP Burst to FLP Burst Period			16		ms
100BASE-TX SIGNAL DETECT TIMING⁽²²⁾ (Refer to Figure 4-21)
T2.21.1	SD Internal Turnon Time				1	ms
T2.21.2	SD Internal Turnoff Time	Default operation Fast link-loss indication enabled⁽²³⁾		250 1.3	300	µs µs
100 Mb/s INTERNAL LOOPBACK TIMING (Refer to Figure 4-22)
T2.22.1	TX_EN to RX_DV Loopback⁽²⁴⁾	100 Mb/s internal loopback mode⁽²⁵⁾			240	ns
10 Mb/s INTERNAL LOOPBACK TIMING (Refer to Figure 4-23)
T2.23.1	TX_EN to RX_DV Loopback	10 Mb/s internal loopback mode⁽²⁶⁾			2	µs
RMII TRANSMIT TIMING (SLAVE MODE) (Refer to Figure 4-24)
T2.24.1	X1 Clock Period	50-MHz Reference Clock		20		ns
T2.24.2	TXD[1:0], TX_EN, Data Setup to X1 rising edge		4
T2.24.3	TXD[1:0], TX_EN, Data Hold from X1 rising edge		2
T2.24.4	X1 Clock to PMD Output Pair Latency (100 Mb)⁽²⁷⁾	100BASE-TX or 100BASE-FX		11		bits
RMII TRANSMIT TIMING (MASTER MODE) (Refer to Figure 4-25)
T2.25.1	RX_CLK, TX_CLK, CLK_OUT Period	50-MHz Reference Clock		20		ns
T2.25.2	TXD[1:0], TX_EN Data Setup to RX_CLK, TX_CLK, CLK_OUT rising edge		4
T2.25.3	TXD[1:0], TX_EN Data Hold from RX_CLK, TX_CLK, CLK_OUT rising edge		2
T2.25.4	RX_CLK, TX_CLK, CLK_OUT to PMD Output Pair Latency⁽²⁸⁾	From RX_CLK rising edge to first bit of symbol		11		bits
RMII RECEIVE TIMING (SLAVE MODE)⁽²⁹⁾ (Refer to Figure 4-26)
T2.26.1	X1 Clock Period	50-MHz Reference Clock		20		ns
T2.26.2	RXD[1:0], CRS_DV, and RX_ER output delay from X1 rising edge⁽³⁰⁾		2		14	ns
T2.26.3	CRS ON delay⁽³¹⁾	100BASE-TX mode		18.5		bits
T2.26.3	CRS ON delay⁽³¹⁾	100BASE-FX mode		9
T2.26.4	CRS OFF delay ⁽³²⁾	100BASE-TX mode		27
T2.26.4	CRS OFF delay ⁽³²⁾	100BASE-FX mode		17
T2.26.5	RXD[1:0] and RX_ER latency⁽³³⁾⁽³⁴⁾⁽³⁵⁾	100BASE-TX mode		38
T2.26.5	RXD[1:0] and RX_ER latency⁽³³⁾⁽³⁴⁾⁽³⁵⁾	100BASE-FX mode		27
RMII RECEIVE TIMING (MASTER MODE)⁽³⁶⁾ (Refer to Figure 4-27)
T2.27.1	RX_CLK, TX_CLK, CLK_OUT Clock Period	50-MHz Reference Clock		20		ns
T2.27.2	RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK, TX_CLK, CLK_OUT rising edge⁽³⁷⁾		2		14	ns
T2.27.3	CRS ON delay⁽³⁸⁾	100BASE-TX mode		18.5		bits
T2.27.3	CRS ON delay⁽³⁸⁾	100BASE-FX mode		9
T2.27.4	CRS OFF delay ⁽³⁹⁾	100BASE-TX mode		27
T2.27.4	CRS OFF delay ⁽³⁹⁾	100BASE-FX mode		17
T2.27.5	RXD[1:0] and RX_ER latency ⁽⁴⁰⁾	100BASE-TX mode		38
T2.27.5	RXD[1:0] and RX_ER latency ⁽⁴⁰⁾	100BASE-FX mode		27
RX_CLK TIMING (RMII MASTER MODE) (Refer to Figure 4-28)
T2.28.1	RX_CLK High Time⁽⁴¹⁾			12		ns
T2.28.2	RX_CLK Low Time⁽⁴¹⁾			8
T2.28.3	RX_CLK Period			20
CLK_OUT TIMING (RMII SLAVE MODE) (Refer to Figure 4-29)
T2.29.1	CLK_OUT High/Low Time			10		ns
T2.29.2	CLK_OUT propagation delay	Relative to X1			8	ns
SINGLE CLOCK MII (SCMII) TRANSMIT TIMING (Refer to Figure 4-30)
T2.30.1	X1 Clock Period	25-MHz Reference Clock		40		ns
T2.30.2	TXD[3:0], TX_EN Data Setup	To X1 rising edge	4
T2.30.3	TXD[3:0], TX_EN Data Hold	From X1 rising edge	2
T2.30.4	X1 Clock to PMD Output Pair Latency (100 Mb)⁽⁴²⁾	100BASE-TX or 100BASE-FX		13		bits
SINGLE CLOCK MII (SCMII) RECEIVE TIMING (Refer to Figure 4-31)
T2.31.1	X1 Clock Period	25-MHz Reference Clock⁽⁴⁴⁾		40		ns
T2.31.2	RXD[3:0], RX_DV and RX_ER output delay⁽⁴³⁾	From X1 rising edge	2		18	ns
T2.31.3	CRS ON delay ⁽⁴⁵⁾	100BASE-TX mode		19		bits
T2.31.3	CRS ON delay ⁽⁴⁵⁾	100BASE-FX mode		9
T2.31.4	CRS OFF delay ⁽⁴⁶⁾	100BASE-TX mode		26
T2.31.4	CRS OFF delay ⁽⁴⁶⁾	100BASE-FX mode		16
T2.31.5	RXD[3:0] and RX_ER latency⁽⁴⁷⁾	100BASE-TX mode		56
T2.31.5	RXD[3:0] and RX_ER latency⁽⁴⁷⁾	100BASE-FX mode		46
100 Mb/s X1 TO TX_CLK TIMING (Refer to Figure 4-32)
T2.32.1	X1 to TX_CLK delay⁽⁴⁸⁾	100 Mb/s Normal mode	0		5	ns

(1) In RMII Slave Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.

(2) It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(5) Enabling PHY Control Frames will add latency equal to 8 bits times the PCF_BUF_SIZE setting. For example if PCF_BUF_SIZE is set to 15, then the additional delay will be 15*8= 120 bits.

(6) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the "T" code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(7) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.

(8) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

(9) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(10) 1 bit time = 10 ns in 100 Mb/s mode.

(11) Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.

(12) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive datapath.

(13) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(14) 1 bit time = 10 ns in 100 Mb/s mode.

(15) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.

(16) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(17) 1 bit time = 100 ns in 10 Mb/s mode.

(18) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV.

(19) 1 bit time = 100 ns in 10 Mb/s mode.

(20) These specifications represent transmit timings.

(21) These specifications represent transmit timings.

(22) The signal amplitude on PMD Input Pair must be TP-PMD compliant.

(23) Fast Link-loss detect is enabled by setting the SD_CNFG[8] register bit to a 1.

(24) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550 µs “dead-time”.

(25) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

(26) Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.

(27) Latency measurement is made from the X1 rising edge to the first bit of symbol.

(28) Latency measurement is made from the RX_CLK rising edge to the first bit of symbol.

(29) Per the RMII Specification, output delays assume a 25-pF load.

(30) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.

(31) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(32) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial deassertion of CRS_DV.

(33) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).

(34) Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.

(35) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive datapath.

(36) Per the RMII Specification, output delays assume a 25-pF load.

(37) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.

(38) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(39) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial deassertion of CRS_DV.

(40) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).

(41) The High Time and Low Tme will add up to 20 ns.

(42) Latency measurement is made from the X1 rising edge to the first bit of symbol.

(43) Output delays assume a 25-pF load.

(44) CRS is asserted and deasserted asynchronously relative to the reference clock.

(45) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.

(46) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to deassertion of CRS_DV.

(47) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).

(48) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data.