SNLS250E May   2008  – April 2015 DP83848H , DP83848J , DP83848K , DP83848M , DP83848T

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Pin Configuration and Functions
    1. 4.1  Pin Diagram
    2. 4.2  Package Pin Assignments
    3. 4.3  Serial Management Interface
    4. 4.4  Mac Data Interface
    5. 4.5  Clock Interface
    6. 4.6  LED Interface
    7. 4.7  Reset
    8. 4.8  Strap Options
    9. 4.9  10 Mb/s and 100 Mb/s PMD Interface
    10. 4.10 Special Connections
    11. 4.11 Power Supply Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Specifications
    6. 5.6 AC Timing Requirements
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Auto-Negotiation
        1. 6.3.1.1 Auto-Negotiation Pin Control
        2. 6.3.1.2 Auto-Negotiation Register Control
        3. 6.3.1.3 Auto-Negotiation Parallel Detection
        4. 6.3.1.4 Auto-Negotiaion Restart
        5. 6.3.1.5 Auto-Negotiation Complete Time
      2. 6.3.2 Auto-MDIX
      3. 6.3.3 LED Interface
        1. 6.3.3.1 LED
        2. 6.3.3.2 LED Direct Control
      4. 6.3.4 Internal Loopback
      5. 6.3.5 BIST
      6. 6.3.6 Energy Detect Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 MII Interface
        1. 6.4.1.1 Nibble-wide MII Data Interface
        2. 6.4.1.2 Collision Detect
        3. 6.4.1.3 Carrier Sense
      2. 6.4.2 Reduced MII Interface
      3. 6.4.3 802.3 MII Serial Management Interface
        1. 6.4.3.1 Serial Management Register Access
        2. 6.4.3.2 Serial Management Access Protocol
        3. 6.4.3.3 Serial Management Preamble Suppression
      4. 6.4.4 PHY Address
        1. 6.4.4.1 MII Isolate Mode
      5. 6.4.5 Half Duplex vs Full Duplex
      6. 6.4.6 Reset Operation
        1. 6.4.6.1 Hardware Reset
        2. 6.4.6.2 Software Reset
      7. 6.4.7 Power Down
    5. 6.5 Programming
      1. 6.5.1 Architecture
        1. 6.5.1.1 100BASE-TX Transmitter
          1. 6.5.1.1.1 Code-Group Encoding and Injection
          2. 6.5.1.1.2 Scrambler
          3. 6.5.1.1.3 NRZ to NRZI Encoder
          4. 6.5.1.1.4 Binary to MLT-3 Convertor
        2. 6.5.1.2 100BASE-TX Receiver
          1. 6.5.1.2.1  Analog Front End
          2. 6.5.1.2.2  Digital Signal Processor
          3. 6.5.1.2.3  Digital Adaptive Equalization and Gain Control
          4. 6.5.1.2.4  Base Line Wander Compensation
          5. 6.5.1.2.5  Signal Detect
          6. 6.5.1.2.6  MLT-3 to NRZI Decoder
          7. 6.5.1.2.7  NRZI to NRZ
          8. 6.5.1.2.8  Serial to Parallel
          9. 6.5.1.2.9  Descrambler
          10. 6.5.1.2.10 Code-Group Alignment
          11. 6.5.1.2.11 4B/5B Decoder
          12. 6.5.1.2.12 100BASE-TX Link Integrity Monitor
          13. 6.5.1.2.13 Bad SSD Detection
        3. 6.5.1.3 10BASE-T Transceiver Module
          1. 6.5.1.3.1  Operational Modes
          2. 6.5.1.3.2  Smart Squelch
          3. 6.5.1.3.3  Collision Detection and SQE
          4. 6.5.1.3.4  Carrier Sense
          5. 6.5.1.3.5  Normal Link Pulse Detection/Generation
          6. 6.5.1.3.6  Jabber Function
          7. 6.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 6.5.1.3.8  Transmit and Receive Filtering
          9. 6.5.1.3.9  Transmitter
          10. 6.5.1.3.10 Receiver
    6. 6.6 Memory
      1. 6.6.1 Register Block
        1. 6.6.1.1 Register Definition
          1. 6.6.1.1.1 Basic Mode Control Register (BMCR)
          2. 6.6.1.1.2 Basic Mode Status Register (BMSR)
          3. 6.6.1.1.3 PHY Identifier Register #1 (PHYIDR1)
          4. 6.6.1.1.4 PHY Identifier Register #2 (PHYIDR2)
          5. 6.6.1.1.5 Auto-Negotiation Advertisement Register (ANAR)
          6. 6.6.1.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
          7. 6.6.1.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
          8. 6.6.1.1.8 Auto-Negotiate Expansion Register (ANER)
          9. 6.6.1.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
        2. 6.6.1.2 Extended Registers
          1. 6.6.1.2.1  PHY Status Register (PHYSTS)
          2. 6.6.1.2.2  False Carrier Sense Counter Register (FCSCR)
          3. 6.6.1.2.3  Receiver Error Counter Register (RECR)
          4. 6.6.1.2.4  100 Mb/s PCS Configuration and Status Register (PCSR)
          5. 6.6.1.2.5  RMII and Bypass Register (RBR)
          6. 6.6.1.2.6  LED Direct Control Register (LEDCR)
          7. 6.6.1.2.7  PHY Control Register (PHYCR)
          8. 6.6.1.2.8  10BASE-T Status/Control Register (10BTSCR)
          9. 6.6.1.2.9  CD Test and BIST Extensions Register (CDCTRL1)
          10. 6.6.1.2.10 Energy Detect Control (EDCR)
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 TPI Network Circuit
        2. 7.2.1.2 Clock IN (X1) Recommendations
          1. 7.2.1.2.1 Oscillator
          2. 7.2.1.2.2 Crystal
        3. 7.2.1.3 Power Feedback Circuit
        4. 7.2.1.4 Magnetics
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 MAC Interface (MII/RMII)
          1. 7.2.2.1.1 Termination Requirement
          2. 7.2.2.1.2 Recommended Maximum Trace Length
        2. 7.2.2.2 Calculating Impedance
          1. 7.2.2.2.1 Microstrip Impedance - Single-Ended
          2. 7.2.2.2.2 Stripline Impedance - Single-Ended
          3. 7.2.2.2.3 Microstrip Impedance - Differential
          4. 7.2.2.2.4 Stripline Impedance - Differential
      3. 7.2.3 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 PCB Layer Stacking
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Related Links
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical Packaging and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

The DP83848x pins are classified into the following interface categories (each interface is described in the sections that follow):

  • Serial Management Interface
  • MAC Data Interface
  • Clock Interface
  • LED Interface
  • Reset
  • Strap Options
  • 10/100 Mb/s PMD Interface
  • Special Connections
  • Power Supply Pins

NOTE

Strapping pin option. See Section 4.8 for strap definitions.

All DP83848x signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.

    Type: IInput
    Type: OOutput
    Type: I/OInput/Output
    Type: ODOpen Drain
    Type: PD,PU Internal Pulldown/Pullup
    Type: SStrapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-kΩ resistor should be used. See Section 4.8 for details.)

4.1 Pin Diagram

RTA Package
40-Pin WQFN
Top View

DP83848H DP83848J DP83848K DP83848M DP83848T pinout_snls250.gif
Pin 21 is the CLK_OUT pin for the DP83848H/M/T.

4.2 Package Pin Assignments

NSQAU040
PIN #		 PIN NAME
(DP83848J)		 NSQAU040
PIN #		 PIN NAME
(DP83848J)
1 IO_VDD 21(1) LED_SPEED/AN1
2 TX_CLK 22 LED_LINK/AN0
3 TX_EN 23 RESET_N
4 TXD_0 24 MDIO
5 TXD_1 25 MDC
6 TXD_2 26 IOVDD33
7 TXD_3 27 X2
8 RESERVED 28 X1
9 RESERVED 29 DGND
10 RESERVED 30 PFBIN2
11 RD– 31 RX_CLK
12 RD+ 32 RX_DV/MII_MODE
13 AGND 33 CRS/CRS_DV/LED_CFG
14 TD – 34 RX_ER/MDIX_EN
15 TD + 35 COL/PHYAD0
16 PFBIN1 36 RXD_0/PHYAD1
17 AGND 37 RXD_1/PHYAD2
18 AVDD33 38 RXD_2/PHYAD3
19 PFBOUT 39 RXD_3/PHYAD4
20 RBIAS 40 IOGND
(1) Pin 21 is the CLK_OUT pin for the DP83848H/M/T.

4.3 Serial Management Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO I/O 24 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor.

4.4 Mac Data Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
COL S, O, PU 35 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half-Duplex Modes.

While in 10BASE-T Half-Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10Mb/s full duplex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.
CRS/CRS_DV S, O, PU 33 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.

RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
RX_CLK O 31 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
RX_DV O, PD 32 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].

RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid indication independent of Carrier Sense.
RX_ER S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RX_DV is asserted in 100 Mb/s mode.

This pin is not required to be used by a MAC, in either MII or RMII mode, because the Phy is required to corrupt data on a receive error.

RXD_0
RXD_1
RXD_2
RXD_3		 S, O, PD 36
37
38
39		 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25-MHz reference clock.

Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive.
TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3		 I
I
I
I, PD		 4
5
6
7		 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock.

4.5 Clock Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
X1 I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848x and must be connected to a 25-MHz 0.005% (+50 ppm) clock source. The DP83848x supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz 0.005% (+50 ppm) CMOS-level oscillator source.
X2 O 27 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25-MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.

4.6 LED Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
LED_LINK S, O, PU 22 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED S, O, PU 21 SPEED LED: This LED is ON when DP83848x is in 100 Mb/s and OFF when DP83848x is in 10 Mb/s. Functionality of this LED is independent of the mode selected.(1)
(1) LED_SPEED only exists in the DP83848J/K. DP83848M/T/H has CLK_OUT on pin 21.

4.7 Reset

SIGNAL NAME TYPE PIN # DESCRIPTION
RESET_N I, PU 23 RESET: Active Low input that initializes or re-initializes the DP83848x. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well.

4.8 Strap Options

DP83848x uses many functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2-kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Because these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

SIGNAL NAME TYPE PIN # DESCRIPTION
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)		 S, O, PU
S, O, PD		 35
36
37
38
39		 PHY ADDRESS [4:0]: The DP83848x provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset.

The DP83848x supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the MII isolate mode. Refer to Section 6.4.4 for additional information.

PHYAD0 pin has weak internal pullup resistor.

PHYAD[4:1] pins have weak internal pulldown resistors.

AN0 (LED_LINK)
AN1 (LED_SPEED)(1)		 S, O, PU
S, O, PU		 22
21		 These input pins control the advertised operating mode of the device according to the following table. The value on these pins are set by connecting them to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins should NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83848x at Hardware-Reset.

The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default for DP83848x is 11 because these pins have an internal pullup.
AN1(1) AN0 Advertised Mode
0 0 10BASE-T, Half/full-Duplex
0 1 100BASE-TX, Half/full-Duplex
1 0 10BASE-T, Half-Duplex
100BASE-TX, Half-Duplex
1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Hal/Full-Duplex
MII_MODE (RX_DV) S, O, PD 32 MII MODE SELECT: This strapping option determines the operating mode of the MAC Data Interface. Default operation (No pullup) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII mode of operation. Because the pin includes an internal pulldown, the default value is 0.

The following table details the configuration:
MIL_MODE MAC Interface Mode
0 MII Mode
1 RMII Mode
LED_CFG
(CRS/CRS_DV)		 S, O, PU 33 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access.

See Table 6-2 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable Auto-MDIX mode.
(1) AN1 (LED_SPEED) is only available on the DP83848J/K.

4.9 10 Mb/s and 100 Mb/s PMD Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
TD-, TD+ I/O 14, 15 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.

These pins require 3.3-V bias for operation.
RD-, RD+ I/O 11, 12 Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.

These pins require 3.3-V bias for operation.

4.10 Special Connections

SIGNAL NAME TYPE PIN # DESCRIPTION
RBIAS I 20 Bias Resistor Connection. A 4.87-kΩ 1% resistor should be connected from RBIAS to GND.
PFBOUT O 19 Power Feedback Output. Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 16) and PFBIN2 (pin 30). See Section 7.2.1.3 for proper placement pin.
PFBIN1
PFBIN2		 I 16
30		 Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin.

Note: Do not supply power to these pins other than from PFBOUT.

RESERVED I/O 8,9,10 RESERVED: These pins must be left unconnected.

4.11 Power Supply Pins

SIGNAL NAME PIN # DESCRIPTION
IOVDD33 1, 26 I/O 3.3-V Supply
IOGND 40 I/O Ground
DGND 29 Digital Ground
AVDD33 18 Analog 3.3-V Supply
AGND 13, 17 Analog Ground