SNLS341C March   2011  – March 2015 DP83848Q-Q1

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1  Pin Layout
    2. 3.2  Package Pin Assignments
    3. 3.3  Serial Management Interface
    4. 3.4  MAC Data Interface
    5. 3.5  Clock Interface
    6. 3.6  LED Interface
    7. 3.7  RESET
    8. 3.8  Strap Options
    9. 3.9  10 Mb/s and 100 Mb/s PMD Interface
    10. 3.10 Special Connections
    11. 3.11 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics: DC
    6. 4.6 Electrical Characteristics: AC
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs. Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  False Carrier Sense Counter Register (FCSCR)
        3. 5.6.2.3  Receiver Error Counter Register (RECR)
        4. 5.6.2.4  100 Mb/s PCS Configuration and Status Register (PCSR)
        5. 5.6.2.5  RMII and Bypass Register (RBR)
        6. 5.6.2.6  LED Direct Control Register (LEDCR)
        7. 5.6.2.7  PHY Control Register (PHYCR)
        8. 5.6.2.8  10 Base-T Status/Control Register (10BTSCR)
        9. 5.6.2.9  CD Test and BIST Extensions Register (CDCTRL1)
        10. 5.6.2.10 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curve
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Pin Configuration and Functions

The DP83848Q-Q1 pins are classified into the following interface categories (each interface is described in the sections that follow):

  • Serial Management Interface
  • MAC Data Interface
  • Clock Interface
  • LED Interface
  • Reset
  • Strap Options
  • 10/100 Mb/s PMD Interface
  • Special Connect Pins
  • Power and Ground pins

All DP83848Q-Q1 signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.

NOTE

Strapping pin option. See Section 3.8 for strap definitions.
    Type: IInput
    Type: OOutput
    Type: I/OInput/Output
    Type: ODOpen Drain
    Type: PD,PU Internal Pulldown/Pullup
    Type: SStrapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap value is to be changed then an external 2.2-kΩ resistor should be used. See Section 3.8 for details.)

3.1 Pin Layout

RTA Package
40-Pin WQFN
See RTA0040A

DP83848Q-Q1 SNLS480_30152555.gif

3.2 Package Pin Assignments

PIN NO. PIN NAME
1 IO_VDD
2 TX_CLK
3 TX_EN
4 TXD_0
5 TXD_1
6 TXD_2
7 TXD_3
8 RESERVED
9 RESERVED
10 RESERVED
11 RD–
12 RD+
13 AGND
14 TD–
15 TD+
16 PFBIN1
17 AGND
18 AVDD33
19 PFBOUT
20 RBIAS
21 CLK_OUT
22 LED_LINK/AN0
23 RESET_N
24 MDIO
25 MDC
26 IOVDD33
27 X2
28 X1
29 DGND
30 PFBIN2
31 RX_CLK
32 RX_DV/MII_MODE
33 CRS/CRS_DV/LED_CFG
34 RX_ER/MDIX_EN
35 COL/PHYAD0
36 RXD_0/PHYAD1
37 RXD_1/PHYAD2
38 RXD_2/PHYAD3
39 RXD_3/PHYAD4
40 IOGND
DAP NC or GND(1)
(1) Die Attach Pad (DAP) provides thermal dissipation. Connection to GND plane recommended.

3.3 Serial Management Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO I/O 24 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

3.4 MAC Data Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3		 I
 
 
I, PD		 4
5
6
7		 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock.
RX_CLK O 31 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
RX_DV S, O, PD 32 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid indication independent of Carrier Sense.
RX_ER S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, because the Phy is required to corrupt data on a receive error.
RXD_0
RXD_1
RXD_2
RXD_3		 S, O, PD 36
37
38
39		 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
CRS/CRS_DV S, O, PU 33 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
COL S, O, PU 35 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.

3.5 Clock Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
X1 I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848Q-Q1 and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848Q-Q1 supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.
X2 O 27 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.
CLK_OUT O 21 MII 25 MHz CLOCK OUTPUT: This pin provides a 25 MHz clock output to the system. This allows other devices to use the reference clock without requiring additional clock sources.
RMII 50 MHz CLOCK OUTPUT: Tthis pin provides a 50 MHz clock output to the system. For RMII mode, it is not recommended that the system clock out be used as the reference clock to the MAC. See SNLA076 for more details.

3.6 LED Interface

See Table 5-2 for LED Mode Selection.
SIGNAL NAME TYPE PIN NO. DESCRIPTION
LED_LINK S, O, PU 22 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.

3.7 RESET

SIGNAL NAME TYPE PIN NO. DESCRIPTION
RESET_N I, PU 23 RESET: Active Low input that initializes or re-initializes the DP83848Q-Q1 . Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Section 5.6. All strap options are re-initialized as well.

3.8 Strap Options

The DP83848Q-Q1 uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Because these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

SIGNAL NAME TYPE PIN NO. DESCRIPTION
PHYAD0 (COL)
PHYAD1 (RXD1_0)
PHYAD2 (RXD0_1)
PHYAD3 (RXD1_2)
PHYAD4 (RXD1_3)		 S, O, PU
S, O, PD		 35
36
37
38
39		 PHY ADDRESS [4:0]: The DP83848Q-Q1 provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset.
The DP83848Q-Q1 supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the Mll isolate mode. Refer to Section 5.4.4 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
AN_0 (LED_LINK) S, O, PU 22 AN0: This input pin controls the advertised operating mode of the DP83848Q-Q1 according to the following table. The value on this pin is set by connecting the input pin to GND (0) or VCC (1) through 2.2 kΩ resistors. This pin should NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848Q-Q1 at Hardware-Reset.
The float/pull-down status of this pin is latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 1 because the this pin has an internal pull-up.  
AN0 Advertised Mode
0 10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
MII_MODE (RX_DV) S, O, PD 32 MII MODE SELECT: This strapping option determines the operating mode of the MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in the RMII mode of operation. Because the pin includes an internal pull-down, the default value is 0.
The following table details the configurations:  
MII_MODE MAC Interface Mode
0 MII Mode
1 RMII Mode
LED_CFG (CRS/CRS_DV) S, O, PU 33 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pin. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access.
See Table 5-2 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable Auto-MDIX mode.

3.9 10 Mb/s and 100 Mb/s PMD Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
TD-, TD+ I/O 14
15		 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.
IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3V bias for operation.
RD-, RD+ I/O 11
12		 Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
These pins require 3.3V bias for operation.

3.10 Special Connections

SIGNAL NAME TYPE PIN NO. DESCRIPTION
RBIAS I 20 Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to GND.
PFBOUT O 19 Power Feedback Output: Parallel caps, 10µF (Tantalum preferred) and 0.1µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 6.2.1.3 for proper placement pin.
PFBIN1
PFBIN2		 I 16
30		 Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1µF should be connected close to each pin.
Note: Do not supply power to these pins other than from PFBOUT.
RESERVED I/O 8, 9, 10 RESERVED: These pins must be left unconnected.

3.11 Power Supply Pins

SIGNAL NAME PIN NO. DESCRIPTION
IOVDD33 1, 26 I/O 3.3-V Supply
IOGND 40 I/O Ground
DGND 29 Digital Ground
AVDD33 18 Analog 3.3-V Supply
AGND 13, 17 Analog Ground
GNDPAD DAP No connect or connect to Ground(1)