SLIS162H December   2014  – August 2018 DRV5013-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Output State
      2.      Device Packages
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Magnetic Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Field Direction Definition
      2. 7.3.2 Device Output
      3. 7.3.3 Power-On Time
      4. 7.3.4 Output Stage
      5. 7.3.5 Protection Circuits
      6. 7.3.6 Overcurrent Protection (OCP)
      7. 7.3.7 Load Dump Protection
      8. 7.3.8 Reverse Supply Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Standard Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Configuration Example
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Two-Wire Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Stage

The DRV5013-Q1 output stage uses an open-drain NMOS, and it is rated to sink up to 30 mA of current. For proper operation, calculate the value of the pullup resistor R1 using Equation 1.

Equation 1. DRV5013-Q1 eq_01_slis150.gif

The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching.

In addition, ensure that the value of R1 > 500 Ω to ensure the output driver can pull the OUT pin close to GND.

NOTE

Vref is not restricted to VCC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings.

DRV5013-Q1 circuit_vref_slis150.gifFigure 17.

Select a value for C2 based on the system bandwidth specifications as shown in Equation 2.

Equation 2. DRV5013-Q1 eq_02_slis150.gif

Most applications do not require this C2 filtering capacitor.