SLOS846C September   2013  – December 2016 DRV8303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Current Shunt Amplifier Characteristics
    7. 6.7 SPI Characteristics (Slave Mode Only)
    8. 6.8 Gate Timing and Protection Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Protection Features
        1. 7.3.3.1 Power Stage Protection
        2. 7.3.3.2 Overcurrent Protection (OCP) and Reporting
        3. 7.3.3.3 Undervoltage Protection (UVLO)
        4. 7.3.3.4 Overvoltage Protection (GVDD_OV)
        5. 7.3.3.5 Overtemperature Protection
        6. 7.3.3.6 Fault and Protection Handling
      4. 7.3.4 Start-Up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
      4. 7.4.4 DC_CAL
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. 7.6.3.1 Status Registers
        2. 7.6.3.2 Control Registers
        3. 7.6.3.3 Overcurrent Adjustment
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Power-Up Sequencing Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCA Package
48-Pin TSSOP Pad Down
Top View
DRV8303 pinout_SLOS846.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 nOCTW O Overcurrent and overtemperature warning indicator. This output is open drain with external pullup resistor required. Programmable output mode through SPI registers.
2 nFAULT O Fault report indicator. This output is open drain with external pullup resistor required.
3 DTC I Dead-time adjustment with external resistor to GND
4 nSCS I SPI chip select
5 SDI I SPI input
6 SDO O SPI output
7 SCLK I SPI clock signal
8 DC_CAL I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.
9 GVDD P Internal gate driver voltage regulator. GVDD cap should connect to GND
10 CP1 P Charge pump pin 1, ceramic cap should be used between CP1 and CP2
11 CP2 P Charge pump pin 2, ceramic cap should be used between CP1 and CP2
12 EN_GATE I Enable gate driver and current shunt amplifiers.
13 INH_A I PWM Input signal (high side), half-bridge A
14 INL_A I PWM Input signal (low side), half-bridge A
15 INH_B I PWM Input signal (high side), half-bridge B
16 INL_B I PWM Input signal (low side), half-bridge B
17 INH_C I PWM Input signal (high side), half-bridge C
18 INL_C I PWM Input signal (low side), half-bridge C
19 DVDD P Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry.
20 REF I Reference voltage to set output of shunt amplifiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller.
21 SO1 O Output of current amplifier 1
22 SO2 O Output of current amplifier 2
23 AVDD P Internal 6-V supply voltage, AVDD capacitor should always be installed and connected to AGND. This is an output, but not specified to drive external circuitry.
24 AGND P Analog ground pin
25 PVDD P Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD cap should connect to GND
26 SP2 I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.
27 SN2 I Input of current amplifier 2 (connecting to negative input of amplifier).
28 SP1 I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.
29 SN1 I Input of current amplifier 1 (connecting to negative input of amplifier).
30 SL_C I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C.
31 GL_C O Gate drive output for Low-Side MOSFET, half-bridge C
32 SH_C I High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD.
33 GH_C O Gate drive output for High-Side MOSFET, half-bridge C
34 BST_C P Bootstrap capacitor pin for half-bridge C
35 SL_B I Low-Side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B.
36 GL_B O Gate drive output for Low-Side MOSFET, half-bridge B
37 SH_B I High-Side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD.
38 GH_B O Gate drive output for High-Side MOSFET, half-bridge B
39 BST_B P Bootstrap cap pin for half-bridge B
40 SL_A I Low-Side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A.
41 GL_A O Gate drive output for Low-Side MOSFET, half-bridge A
42 SH_A I High-Side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and PVDD.
43 GH_A O Gate drive output for High-Side MOSFET, half-bridge A
44 BST_A P Bootstrap capacitor pin for half-bridge A
45 VDD_SPI I SPI supply pin to support 3.3V or 5V logic. Connect to either 3.3V or 5V.
469 GND O GND pin. The exposed power pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading.
47
48
49 GND
(PWR_PAD)