SLVS913E January   2009  – January 2016 DRV8823

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
      2. 7.4.2 Current Regulation
      3. 7.4.3 Blanking Time
      4. 7.4.4 Decay Mode
      5. 7.4.5 Protection Circuits
        1. 7.4.5.1 OCP
        2. 7.4.5.2 Thermal Shutdown (TSD)
        3. 7.4.5.3 Undervoltage Lockout (UVLO)
        4. 7.4.5.4 Shoot-Through Current Prevention
      6. 7.4.6 Serial Data Transmission
      7. 7.4.7 Data Format
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
      3. 8.2.3 Drive Current
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Small-value capacitors should be ceramic, and placed closely to device pins.

The high-current device outputs should use wide metal traces.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the I2 × RDS(on) heat that is generated in the device.

10.2 Layout Example

DRV8823 layout_slvs913.gif Figure 20. Typical Layout of DRV8823

10.3 Thermal Considerations

The DRV8823 has TSD as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

10.3.1 Power Dissipation

Power dissipation in the DRV8823 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 3.

Equation 3. DRV8823 equat2_lvs912.gif

where

  • PTOT is the total power dissipation.
  • RDS(ON) is the resistance of each FET.
  • IOUT(RMS) is the RMS output current being applied to each winding.

IOUT(RMS) is equal to approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high side and one low side). Remember that the DRV8823 has two stepper motor drivers, so the power dissipation of each must be added together to determine the total device power dissipation.

The maximum amount of power that can be dissipated in the DRV8823 depends on ambient temperature and heatsinking. Use the thermal Dissipation Ratings to estimate the temperature rise for typical PCB constructions.

Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when sizing the heatsink.

10.3.2 Heatsinking

The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For details about how to design the PCB, refer to TI application report, PowerPAD™ Thermally Enhanced Package (SLMA002) and TI application brief, PowerPAD™ Made Easy, (SLMA004) available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated. Figure 21 shows thermal resistance versus copper plane area for both a single-sided PCB with 2-oz copper heatsink area, and a 4-layer PCB with 1-oz copper and a solid ground plane. Both PCBs are 76 mm × 114 mm, and 1.6-mm thick. The heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.

Six pins on the center of each side of the package are also connected to the device ground. A copper area can be used on the PCB that connects to the PowerPAD as well as to all the ground pins on each side of the device. This is especially useful for single-layer PCB designs.

DRV8823 thermvcopper_lvs913.gif Figure 21. Thermal Resistance vs Copper Plane Area