SLVSB18H March   2012  – August 2016 DRV8835


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Protection Circuits
        1. Overcurrent Protection (OCP)
        2. Thermal Shutdown (TSD)
        3. Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
      2. 7.4.2 Sleep Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Motor Voltage
        2. Lower-Power Operation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supplies and Input Pins
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace.

The VM pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace. The VM pin must bypass to ground using an appropriate bulk capacitor. This component can be an electrolytic and should be located close to the DRV8835.

10.2 Layout Example

DRV8835 layout_slvsb18.gif Figure 8. Layout Recommendation

10.3 Thermal Considerations

The DRV8835 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or excessively high ambient temperature.

10.3.1 Power Dissipation

Power dissipation in the DRV8835 is dominated by the power dissipated in the output FET resistance, or RDS(on). Average power dissipation when running both H-bridges can be roughly estimated by Equation 1:

Equation 1. PTOT = 2 × RDS(ON) × (IOUT(RMS))2


  • PTOT is the total power dissipation, RDS(ON) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7× the full-scale output current setting. The factor of 2 comes from the fact that there are two H-bridges.

The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking.


RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Consider this increase when sizing the heatsink.

The power dissipation of the DRV8835 is a function of RMS motor current and the resistance of each FET (RDS(ON)), see Equation 2.

Equation 2. Power ≈ IRMS2 × (High-Side RDS(on)+ Low-Side RDS(on))

For this example, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the sum of RDS(on) is about 1 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat will be 0.8 A2 × 1 Ω = 0.64 W.

The temperature that the DRV8835 reaches depends on the thermal resistance to the air and PCB. It is important to solder the device thermal pad to the PCB ground plane, with vias to the top and bottom board layers, in order dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8835 had an effective thermal resistance RθJA of 47°C/W, and as shown in Equation 3.

Equation 3. TJ = TA + (PD × RθJA) = 35°C + (0.64 W × 47°C/W) = 65°C

10.3.2 Heatsinking

The package uses an exposed pad to remove heat from the device. For proper operation, this pad must thermally connect to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For more PCB design details, refer to QFN/SON PCB Attachment and AN-1187 Leadless Leadframe Package (LLP), available at

In general, the more copper area that is provided, the more power can be dissipated.