SLVSFV6 Data sheet

SLVSFV6B August 2022 – October 2023 DRV8962

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DDW|44
- MPDS309B
DDV|44
- MPDS169G

Thermal pad, mechanical data (Package|Pins)

DDW|44
- PPTD374

Orderable Information

6.5 Electrical Characteristics

Typical values are at T_A = 25°C and V_VM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VM, DVDD)
I_VM	VM operating supply current	nSLEEP = 1, No load, VCC = External 5 V		4	7	mA
I_VM	VM operating supply current	nSLEEP = 1, No load, VCC = DVDD		6	9	mA
I_VMQ	VM sleep mode supply current	nSLEEP = 0		3	8	μA
t_SLEEP	Sleep time	nSLEEP = 0 to sleep-mode	120			μs
t_RESET	nSLEEP reset pulse	nSLEEP low to clear fault	20		40	μs
t_WAKE	Wake-up time	nSLEEP = 1 to output transition		0.85	1.2	ms
t_ON	Turn-on time	VM > UVLO to output transition		0.85	1.3	ms
V_DVDD	Internal regulator voltage	No external load, 6 V < V_VM < 65 V	4.75	5	5.25	V
V_DVDD	Internal regulator voltage	No external load, V_VM = 4.5 V	4.35	4.45		V
CHARGE PUMP (VCP, CPH, CPL)
V_VCP	VCP operating voltage	6 V < V_VM < 65 V		V_VM + 5		V
f_(VCP)	Charge pump switching frequency	V_VM > UVLO; nSLEEP = 1		360		kHz
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, EN1, EN2, EN3, EN4, MODE, OCPM, nSLEEP)
V_IL	Input logic-low voltage		0		0.6	V
V_IH	Input logic-high voltage		1.5		5.5	V
V_HYS	Input logic hysteresis (all pins except nSLEEP)			100		mV
V_{HYS_nSLEEP}	nSLEEP logic hysteresis			300		mV
I_IL	Input logic-low current	V_IN = 0 V	–1		1	μA
I_IH	Input logic-high current	V_IN = DVDD			50	μA
t₁	ENx high to OUTx high delay	INx = 1			2	μs
t₂	ENx low to OUTx low delay	INx = 1			2	μs
t₃	ENx high to OUTx low delay	INx = 0			2	μs
t₄	ENx low to OUTx high delay	INx = 0			2	μs
t₅	INx high to OUTx high delay			600		ns
t₆	INx low to OUTx low delay			600		ns
CONTROL OUTPUTS (nFAULT)
V_OL	Output logic-low voltage	I_O = 5 mA			0.35	V
I_OH	Output logic-high leakage		–1		1	μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
R_DS(ONH)	High-side FET on resistance	T_J = 25 °C, I_O = -5 A		53	62	mΩ
		T_J = 125 °C, I_O = -5 A		70	101	mΩ
		T_J = 150 °C, I_O = -5 A		80	112	mΩ
R_DS(ONL)	Low-side FET on resistance	T_J = 25 °C, I_O = 5 A		53	62	mΩ
		T_J = 125 °C, I_O = 5 A		70	101	mΩ
		T_J = 150 °C, I_O = 5 A		80	112	mΩ
t_RF	Output rise/fall time	I_O = 5 A, MODE = 1, between 10% and 90%		70		ns
t_RF	Output rise/fall time	I_O = 5 A, MODE = 0, between 10% and 90%		140		ns
t_D	Output dead time	VM = 24 V, I_O = 5 A		300		ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)
A_IPROPI	Current mirror gain			212		μA/A
A_ERR	Current mirror scaling error	10% to 20% rated current	-8		8	%
		20% to 40% rated current	-5		5
		40% to 100% rated current	-3.5		3.5
I_VREF	VREF Leakage Current	VREF = 3.3 V			50	nA
t_OFF	PWM off-time			17		μs
t_DEG	Current regulation deglitch time			0.5		μs
t_BLK	Current Regulation Blanking time			1.5		μs
t_DELAY	Current sense delay time			2		μs
PROTECTION CIRCUITS
V_UVLO	VM UVLO lockout	VM falling	4.1	4.23	4.35	V
V_UVLO	VM UVLO lockout	VM rising	4.2	4.35	4.46	V
VCC_UVLO	VCC UVLO lockout	VCC falling	2.7	2.8	2.9	V
VCC_UVLO	VCC UVLO lockout	VCC rising	2.8	2.92	3.05	V
V_UVLO,HYS	Undervoltage hysteresis	Rising to falling threshold		120		mV
V_CPUV	Charge pump undervoltage	VCP falling		V_VM + 2		V
I_OCP	Overcurrent protection	Current through any FET, DDW Package	8			A
I_OCP	Overcurrent protection	Current through any FET, DDV Package	16			A
t_OCP	Overcurrent detection delay			2.2		μs
t_RETRY	Overcurrent retry time			4.1		ms
T_OTSD	Thermal shutdown	Die temperature T_J	150	165	180	°C
T_{HYS_OTSD}	Thermal shutdown hysteresis	Die temperature T_J		20		°C

Figure 6-1 IPROPI Timing Diagram