SNLS450A
January 2014 – June 2015
DS125DF111
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration And Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Device Data Path Operation
7.3.1.1
Input Channel Equalization
7.3.1.2
Clock and Data Recovery
7.3.1.3
PRBS Pattern Generator
7.3.1.4
Datapath Multiplexer and Output Driver
7.3.1.5
Reference Clock
7.3.1.6
Control Pins
7.3.1.6.1
Pin Mode Limitation
7.3.1.7
Eye Opening Monitor
7.4
Device Functional Modes
7.4.1
Control Pin Mode
7.4.2
SMBus Master Mode and SMBus Slave Mode
7.5
Programming
7.5.1
SMBus Interface
7.5.1.1
Address Lines
7.5.1.2
Device Configuration in SMBus Slave Mode
7.5.1.3
Bit Fields in the Register Set
7.5.1.4
Writing To and Reading from the Control/Shared Registers
7.5.1.5
SMBus Strap Observation
7.5.1.6
Interrupt Channel Flag Bits
7.5.1.7
Control/Shared Register Reset
7.5.1.8
Device Revision and Device ID
7.5.1.9
Channel Select Register
7.5.1.10
Resetting Individual Channels of the Retimer
7.5.1.11
Rate and Subrate Setting
7.5.1.12
Overriding the CTLE Boost Setting
7.5.1.13
Overriding the Output Multiplexer
7.5.1.14
Overriding the VCO Divider Selection
7.5.1.15
Using the Internal Eye Opening Monitor
7.5.1.16
Overriding the DFE Tap Weights and Polarities
7.5.1.17
Enabling Slow Rise/Fall Time on the Output Driver
7.5.1.18
Using the PRBS Generator
7.5.1.19
Inverting the Output Polarity
7.5.1.20
Figure of Merit Adaption
7.5.1.21
Setting the Rate and Subrate for Lock Acquisition
7.5.1.22
Setting the Adaption/Lock Mode
7.5.1.23
Initiating Adaption
7.5.1.24
Overriding the CTLE Settings Used for CTLE Adaption
7.5.1.25
Setting the Output Differential Voltage
7.5.1.26
Setting the Output De-Emphasis Setting
7.5.1.27
CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges
7.6
Register Maps
7.6.1
Reading To and Writing from the Channel Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.2.3.1
SFF-8431 Testing
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RTW|24
QFND450A
Orderable Information
snls450a_oa
snls450a_pm
Figure 12. DS125DF111 Power Supply and Regulator Connections