SNLS538B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABW|135
  • ABV|135
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DS280DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.

Each channel of the DS280DF810 independently locks to serial data rates in a continuous range from 20.2Gbps to 28.4Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.1376Gbps, 10.3125Gbps, and 12.5Gbps, which allows the DS280DF810 to support individual lane Forward Error Correction (FEC) pass-through.

Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS280DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.

The advanced equalization features of the DS280DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is an excellent choice for front-port optical module applications to reset the jitter budget and retimer the high-speed serial data. The DS280DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.

The DS280DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator and checker allow for in-system diagnostics.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
DS280DF810 ABV (fcBGA, 135) 13mm × 8mm
ABW (fcBGA, 135) 13mm × 8mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.