SNLS144J June   2005  – January 2016 DS40MB200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CML Inputs and EQ
      2. 8.3.2 Multiplexer and Loopback Control
      3. 8.3.3 CML Drivers and Pre-Emphasis Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 1-Gbps to 4-Gbps Low Jitter Operation
  • Fixed Input Equalization
  • Programmable Output Pre-Emphasis
  • Independent Switch and Line Side Pre-Emphasis Controls
  • Programmable Switch-Side Loopback Mode
  • On-Chip Terminations
  • 3.3-V Supply
  • ESD Rating of 6-kV HBM
  • 48-leadless WQFN Package (7 mm × 7 mm)
  • 0°C to +85°C Operating Temperature Range

2 Applications

  • Backplane or Cable Driver
  • Redundancy and Signal Conditioning Applications
  • XAUI

3 Description

The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces.

All output drivers have four selectable steps of pre-emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS40MB200 WQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

DS40MB200 20021733.gif
All CML inputs and outputs must be AC coupled for optimal performance.