SNLS144K June   2005  – March 2024 DS40MB200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CML Inputs and EQ
      2. 7.3.2 Multiplexer and Loopback Control
      3. 7.3.3 CML Drivers and Pre-Emphasis Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
LVCMOS DC SPECIFICATIONS
VIHHigh level input voltage2VCC + 0.3V
VILLow level input voltage−0.30.8V
IIHHigh level input currentVIN = VCC−1010µA
IILLow level input currentVIN = GND7594124µA
RPUPull-high resistance35kΩ
RECEIVER SPECIFICATIONS
VIDDifferential input voltage rangeAC-coupled differential signal.
This parameter is not production tested.		Below 1.25 Gbps1001750mVP-P
At 1.25 Gbps–3.125 Gbps1001560
Above 3.125 Gbps1001200
VICMCommon mode voltage at receiver inputsMeasured at receiver inputs reference to ground.1.3V
RITDInput differential terminationOn-chip differential termination between IN+ or IN−.84100116Ω
DRIVER SPECIFICATIONS
VODBOutput differential voltage swing without pre-emphasisRL = 100 Ω ±1%
PRES_1 = PRES_0 = 0
PREL_1 = PREL_0 = 0
Driver pre-emphasis disabled.
Running K28.7 pattern at 4 Gbps.
See AC Test Circuit for test circuit.		100012001400mVP-P
VPEOutput pre-emphasis voltage ratio
20 × log (VODPE / VODB)		RL = 100 Ω ±1%
Running K28.7 pattern at
4 Gbps(2)
x = S for switch side pre-emphasis control
x = L for line side pre-emphasis control
See Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) on waveform.
See AC Test Circuit for test circuit.		PREx_[1:0] = 000dB
PREx_[1:0] = 01−3
PREx_[1:0] = 10−6
PREx_[1:0] = 11−9
tPEPre-emphasis width(3)Tested at −9-dB pre-emphasis level, PREx[1:0] = 11
x = S for switch side pre-emphasis control
x = L for line side pre-emphasis control
See Test Condition for Output Pre-Emphasis Duration on measurement condition.		125200250ps
ROTSEOutput terminationOn-chip termination from OUT+ or OUT− to VCC(4)425058Ω
ROTDOutput differential terminationOn-chip differential termination between OUT+ and OUT−(4)100Ω
ΔROTSEMismatch in output termination resistorsMismatch in output terminations at OUT+ and OUT−(4)5%
VOCMOutput common mode voltage2.7V
POWER DISSIPATION
PDPower dissipationVDD = 3.465 V
All outputs terminated by 100 Ω ±1%.
PREL_[1:0] = 0, PRES_[1:0] = 0
Running PRBS 27–1 pattern at 4 Gbps		1W
AC CHARACTERISTICS
RJDevice random jitter(5)(3)See AC Test Circuit for test circuit.
Alternating-1-0 pattern.
Pre-emphasis disabled.		At 1.25 Gbps2psrms
At 4 Gbps2
DJDevice deterministic jitter(6)(3)See AC Test Circuit for test circuit.
Pre-emphasis disabled.		At 4 Gbps,
PRBS7 pattern		30psp-p
DRMAXMaximum data rate(3)Tested with alternating-1-0 pattern4Gbps
(1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested.
(2) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and –K28.5 code groups {110000 0101 001111 1010}
(3) Specified by design and characterization using statistical analysis.
(4) IN+ and IN− are generic names refer to one of the many pairs of complementary inputs of the DS40MB200. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS40MB200. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|.
(5) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt (RJOUT2 – RJIN2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device.
(6) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT – DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peak-to-peak deterministic jitter of the pattern generator driving the device.