SNLS477B October 2014 – November 2018 DS90UB948-Q1
The DS90UB948-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different mapping schemes, shown in Figure 33 and Figure 34. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from CLK1± and CLK2± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MODE_SEL0 pin or by Register (Register Maps).