SLVSGV3A April   2022  – July 2022 ESD341

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1.     Absolute Maximum Ratings
    2. 6.1 ESD Ratings—JEDEC Specification
    3. 6.2 ESD Ratings—IEC Specification
    4.     Recommended Operating Conditions
    5. 6.3 Thermal Information
    6. 6.4 Electrical Characteristics
    7. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 DC Breakdown Voltage
      5. 7.3.5 Ultra Low Leakage Current
      6. 7.3.6 Low ESD Clamping Voltage
      7. 7.3.7 Supports High Speed Interfaces
      8. 7.3.8 Industrial Temperature Range
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPL|2
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

  • The optimum placement of the ESD protection device is as close to the connector as possible
    • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures
    • The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector
  • Route the protected traces as straight as possible
  • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible
    • Electric fields tend to build up on corners, increasing EMI coupling
  • If pin 1 or pin 2 is connected to ground, use a thick and short trace for this return path