SPRS825E October   2012  – December 2017 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
        4. 5.9.2.4 Internal Clock Frequencies
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing - Master Subsystem
      5. 5.9.5 Flash Timing - Control Subsystem
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
        2. 5.9.6.2 GPIO - Input Timing
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
      7. 5.9.7 External Interrupt Electrical Data and Timing
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
        4. 5.11.6.4 MDIO Electrical Data and Timing
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. 5.12.1.2.1 Trip-Zone Input Timing
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
          2. 5.12.6.2.2 Slave Mode Timing
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|289
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

The Concerto MCU comprises three subsystems: the Master Subsystem, the Control Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and peripherals, they can also share data and events through shared memories and peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other events to initialize subsystem processors and the rest of the chip to a known state. The Clocking Blocks support multiple low-power modes where clocks to the processors and peripherals can be slowed down or stopped in order to manage power consumption.

NOTE

Throughout this document, the Master Subsystem is denoted by the color blue; the Control Subsystem is denoted by the color green; and the Analog Subsystem is denoted by the color orange.

Memory Maps

Section 6.1.1 shows the Control Subsystem Memory Map. Section 6.1.2 shows the Master Subsystem Memory Map.

Control Subsystem Memory Map

Table 6-1 Control Subsystem M0, M1 RAM

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM M0, M1 RAM SIZE
(BYTES)
no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K
no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K
The letter "C" refers to the Control Subsystem.

Table 6-2 Control Subsystem Peripheral Frame 0

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 0
(INCLUDES ANALOG)
SIZE
(BYTES)
0000 0800 – 0000 087F Reserved
no 0000 0880 – 0000 0890 Control Subsystem Device Configuration Registers (Read Only) 34
0000 0891 – 0000 0ADF Reserved
no 0000 0AE0 – 0000 0AEF C28x CSM Registers 32
0000 0AF0 – 0000 0AFF Reserved
yes 0000 0B00 – 0000 0B0F ADC1 Result Registers 32
0000 0B10 – 0000 0B3F Reserved
yes 0000 0B40 – 0000 0B4F ADC2 Result Registers 32
0000 0B50 – 0000 0BFF Reserved
no 0000 0C00 – 0000 0C07 CPU Timer 0 16
no 0000 0C08 – 0000 0C0F CPU Timer 1 16
no 0000 0C10 – 0000 0C17 CPU Timer 2 16
0000 0C18 – 0000 0CDF Reserved
no 0000 0CE0 – 0000 0CFF PIE Registers 64
no 0000 0D00 – 0000 0DFF PIE Vector Table 512
no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512
0000 0F00 – 0000 0FFF Reserved
no 0000 1000 – 0000 11FF C28x DMA Registers 1K
0000 1200 – 0000 16FF Reserved
no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256
no 0000 1780 – 0000 17FF Hardware BIST Registers 256
0000 1800 – 0000 3FFF Reserved
The letter "C" refers to the Control Subsystem.

Table 6-3 Control Subsystem Peripheral Frame 3

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM
PERIPHERAL FRAME 3
SIZE
(BYTES)
M ADDRESS
(BYTE-ALIGNED)(2)
µDMA ACCESS
no 0000 4000 – 0000 4181 C28x Flash Control Registers 772
0000 4182 – 0000 42FF Reserved
no 0000 4300 – 0000 4323 C28x Flash ECC Error Log Registers 72
0000 4324 – 0000 43FF Reserved
no 0000 4400 – 0000 443F M Clock Control Registers(2) 128 400F B800 – 400F B87F no
0000 4440 – 0000 48FF Reserved
no 0000 4900 – 0000 497F RAM Configuration Registers 256 400F B200 – 400F B2FF no
0000 4980 – 0000 49FF Reserved
no 0000 4A00 – 0000 4A7F RAM ECC/Parity/Access Error Log Registers 256 400F B300 – 400F B3FF no
0000 4A80 – 0000 4DFF Reserved
no 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 128 400F B700 – 400F B77F no
0000 4E40 – 0000 4FFF Reserved
yes 0000 5000 – 0000 503F McBSP-A 128
0000 5040 – 0000 50FF Reserved
yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256
yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256
yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256
yes 0000 5280 – 0000 52FF EPWM4 (Hi-Resolution) 256
yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256
yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256
yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256
yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256
yes 0000 5500 – 0000 557F EPWM9 256
yes 0000 5580 – 0000 55FF EPWM10 256
yes 0000 5600 – 0000 567F EPWM11 256
yes 0000 5680 – 0000 56FF EPWM12 256
0000 5700 – 0000 57FF Reserved
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.

Table 6-4 Control Subsystem Peripheral Frame 1

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 1 SIZE
(BYTES)
0000 5800 – 0000 59FF Reserved
no 0000 5A00 – 0000 5A1F ECAP1 64
no 0000 5A20 – 0000 5A3F ECAP2 64
no 0000 5A40 – 0000 5A5F ECAP3 64
no 0000 5A60 – 0000 5A7F ECAP4 64
no 0000 5A80 – 0000 5A9F ECAP5 64
no 0000 5AA0 – 0000 5ABF ECAP6 64
0000 5AC0 – 0000 5AFF Reserved
no 0000 5B00 – 0000 5B3F EQEP1 128
no 0000 5B40 – 0000 5B7F EQEP2 128
no 0000 5B80 – 0000 5BBF EQEP3 128
0000 5BC0 – 0000 5EFF Reserved
no 0000 5F00 – 0000 5FFF C GPIO Group 1 Registers(1) 512
0000 6000 – 0000 63FF Reserved
no 0000 6400 – 0000 641F COMP1 Registers 64
no 0000 6420 – 0000 643F COMP2 Registers 64
no 0000 6440 – 0000 645F COMP3 Registers 64
no 0000 6460 – 0000 647F COMP4 Registers 64
no 0000 6480 – 0000 649F COMP5 Registers 64
no 0000 64A0 – 0000 64BF COMP6 Registers 64
0000 64C0 – 0000 6F7F Reserved
no 0000 6F80 – 0000 6FFF C GPIO Group 2 Registers and AIO Mux Registers(1) 256
The letter "C" refers to the Control Subsystem.

Table 6-5 Control Subsystem Peripheral Frame 2

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 2 SIZE
(BYTES)
0000 7000 – 0000 70FF Reserved
no 0000 7010 – 0000 702F C28x System Control Registers 64
0000 7030 – 0000 703F Reserved
no 0000 7040 – 0000 704F SPI-A 32
no 0000 7050 – 0000 705F SCI-A 32
no 0000 7060 – 0000 706F NMI Watchdog Interrupt Registers 32
no 0000 7070 – 0000 707F External Interrupt Registers 32
0000 7080 – 0000 70FF Reserved
no 0000 7100 – 0000 717F ADC1 Configuration Registers
(Only 16-bit read/write access supported)
256
no 0000 7180 – 0000 71FF ADC2 Configuration Registers
(Only 16-bit read/write access supported)
256
0000 7200 – 0000 78FF Reserved
no 0000 7900 – 0000 793F I2C-A 128
0000 7940 – 0000 7FFF Reserved
The letter "C" refers to the Control Subsystem.

Table 6-6 Control Subsystem RAMs

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM RAMS SIZE
(BYTES)
M ADDRESS
(BYTE-ALIGNED)(2)
µDMA ACCESS
no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K
no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K
yes 0000 A000 – 0000 AFFF L2 RAM (Parity) 8K
yes 0000 B000 – 0000 BFFF L3 RAM (Parity) 8K
yes 0000 C000 – 0000 CFFF S0 RAM (Parity, Shared) 8K 2000 8000 – 2000 9FFF yes
yes 0000 D000 – 0000 DFFF S1 RAM (Parity, Shared) 8K 2000 A000 – 2000 BFFF yes
yes 0000 E000 – 0000 EFFF S2 RAM (Parity, Shared) 8K 2000 C000 – 2000 DFFF yes
yes 0000 F000 – 0000 FFFF S3 RAM (Parity, Shared) 8K 2000 E000 – 2000 FFFF yes
yes 0001 0000 – 0001 0FFF S4 RAM (Parity, Shared) 8K 2001 0000 – 2001 1FFF yes
yes 0001 1000 – 0001 1FFF S5 RAM (Parity, Shared) 8K 2001 2000 – 2001 3FFF yes
yes 0001 2000 – 0001 2FFF S6 RAM (Parity, Shared) 8K 2001 4000 – 2001 5FFF yes
yes 0001 3000 – 0001 3FFF S7 RAM (Parity, Shared) 8K 2001 6000 – 2001 7FFF yes
0001 4000 – 0003 F7FF Reserved
yes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF yes
read only
yes
read only
0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yes
0004 0000 – 0004 7FFF Reserved
no 0004 8000 – 0004 8FFF L0 RAM - ECC Bits 8K
no 0004 9000 – 0004 9FFF L1 RAM - ECC Bits 8K
no 0004 A000 – 0004 AFFF L2 RAM - Parity Bits 8K
no 0004 B000 – 0004 BFFF L3 RAM - Parity Bits 8K
no 0004 C000 – 0004 CFFF S0 RAM - Parity Bits 8K 2008 8000 – 2008 9FFF no
no 0004 D000 – 0004 DFFF S1 RAM - Parity Bits 8K 2008 A000 – 2008 BFFF no
no 0004 E000 – 0004 EFFF S2 RAM - Parity Bits 8K 2008 C000 – 2008 DFFF no
no 0004 F000 – 0004 FFFF S3 RAM - Parity Bits 8K 2008 E000 – 2008 FFFF no
no 0005 0000 – 0005 0FFF S4 RAM - Parity Bits 8K 2009 0000 – 2009 1FFF no
no 0005 1000 – 0005 1FFF S5 RAM - Parity Bits 8K 2009 2000 – 2009 3FFF no
no 0005 2000 – 0005 2FFF S6 RAM - Parity Bits 8K 2009 4000 – 2009 5FFF no
no 0005 3000 – 0005 3FFF S7 RAM - Parity Bits 8K 2009 6000 – 2009 7FFF no
0005 4000 – 0007 EFFF Reserved
no 0007 F000 – 0007 F3FF M0 RAM - ECC Bits 2K
no 0007 F400 – 0007 F7FF M1 RAM - ECC Bits 2K
no 0007 F800 – 0007 FBFF CtoM MSG RAM - Parity Bits 2K 200F F000 – 200F F7FF no
no 0007 FC00 – 0007 FFFF MtoC MSG RAM - Parity Bits 2K 200F F800 – 200F FFFF no
0008 0000 – 0009 FFFF Reserved
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.

Table 6-7 Control Subsystem Flash, ECC, OTP, Boot ROM

C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)
CONTROL SUBSYSTEM
FLASH, ECC, OTP,
BOOT ROM
SIZE
(BYTES)
M ADDRESS
(BYTE-ALIGNED)(2)
µDMA ACCESS
no 0010 0000 – 0010 1FFF Sector N (not available for 256KB Flash configuration) 16K
no 0010 2000 – 0010 3FFF Sector M (not available for 256KB Flash configuration) 16K
no 0010 4000 – 0010 5FFF Sector L (not available for 256KB Flash configuration) 16K
no 0010 6000 – 0010 7FFF Sector K (not available for 256KB Flash configuration) 16K
no 0010 8000 – 0010 FFFF Sector J (not available for 256KB Flash configuration) 64K
no 0011 0000 – 0011 7FFF Sector I (not available for 256KB Flash configuration) 64K
no 0011 8000 – 0011 FFFF Sector H (not available for 256KB Flash configuration) 64K
no 0012 0000 – 0012 7FFF Sector G 64K
no 0012 8000 – 0012 FFFF Sector F 64K
no 0013 0000 – 0013 7FFF Sector E 64K
no 0013 8000 – 0013 9FFF Sector D 16K
no 0013 A000 – 0013 BFFF Sector C 16K
no 0013 C000 – 0013 DFFF Sector B 16K
no 0013 E000 – 0013 FFFF Sector A
(CSM password in the high address)
16K
0014 0000 – 001F FFFF Reserved
no 0020 0000 – 0020 7FFF Flash - ECC Bits
(1/8 of Flash used = 64KB)
64K
0020 8000 – 0024 01FF Reserved
no 0024 0200 – 0024 03FF TI one-time programmable (OTP) memory 1K
0024 0400 – 002F FFFF Reserved
yes 0030 0000 – 003F 7FFF EPI0
(External Peripheral/Memory Interface)(3)
2G 6000 0000 – DFFF FFFF yes
no 003F 8000 – 003F FFFF C28x Boot ROM (64KB) 64K
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.

Master Subsystem Memory Map

Table 6-8 Master Subsystem Flash, ECC, OTP, Boot ROM

µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)
MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM SIZE
(BYTES)
no 0000 0000 – 0000 FFFF Boot ROM - Dual-mapped to 0x0100 0000
(Both maps access same physical location.)
64K
0001 0000 – 001F FFFF Reserved
no 0020 0000 – 0020 7FFF Sector N
(Zone 1 CSM password in the low address.)
32K
no 0020 8000 – 0020 FFFF Sector M 32K
no 0021 0000 – 0021 7FFF Sector L 32K
no 0021 8000 – 0021 FFFF Sector K 32K
no 0022 0000 – 0023 FFFF Sector J (not available for 256KB Flash configuration) 128K
no 0024 0000 – 0025 FFFF Sector I (not available for 256KB or 512KB Flash configurations) 128K
no 0026 0000 – 0027 FFFF Sector H (not available for 256KB or 512KB Flash configurations) 128K
no 0028 0000 – 0029 FFFF Sector G (not available for 256KB or 512KB Flash configurations) 128K
no 002A 0000 – 002B FFFF Sector F (not available for 256KB or 512KB Flash configurations) 128K
no 002C 0000 – 002D FFFF Sector E (not available for 256KB Flash configuration) 128K
no 002E 0000 – 002E 7FFF Sector D 32K
no 002E 8000 – 002E FFFF Sector C 32K
no 002F 0000 – 002F 7FFF Sector B 32K
no 002F 8000 – 002F FFFF Sector A
(Zone 2 CSM password in the high address.)
32K
0030 0000 – 005F FFFF Reserved
no 0060 0000 – 0061 FFFF Flash - ECC Bits
(1/8 of Flash used = 128KB)
128K
0062 0000 – 0068 047F Reserved
no 0068 0480 – 0068 0FFF TI OTP 2944
no 0068 1000 OTP – Security Lock 4
0068 1004 Reserved
0068 1008 Reserved
no 0068 100C OTP – Zone 2 Flash Start Address 4
no 0068 1010 OTP – Ethernet Media Access Controller (EMAC) Address 0 4
no 0068 1014 OTP – EMAC Address 1 4
no 0068 1018 Reserved
no 0068 101C OTP – Main Oscillator Clock Frequency 4
0068 0820 – 0070 01FF Reserved
no 0070 0200 – 0070 0203 OTP – ECC Bits – Application Use
(1/8 of OTP used = 3 Bytes)
4
0070 0204 – 00FF FFFF Reserved
no 0100 0000 – 0100 FFFF Boot ROM – Dual-mapped to 0x0000 0000
(Both maps access same physical location.)
64K
0101 0000 – 03FF FFFF Reserved
no 0400 0000 – 07FF FFFF ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC.
Accessing this area of memory by the µCRC peripheral will cause an access in 0000 0000 – 03FF FFFF memory space.
Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped ROM address)
Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF
Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF
(Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register, when reading a block of data.)
64M
0800 0000 – 1FFF FFFF Reserved
The letter "M" refers to the Master Subsystem.

Table 6-9 Master Subsystem RAMs

µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)
MASTER SUBSYSTEM RAMS SIZE
(BYTES)
C ADDRESS
(x16 ALIGNED)(2)
C DMA ACCESS(2)
no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K
no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K
yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K
yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K
yes 2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF yes
yes 2000 A000 – 2000 BFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF yes
yes 2000 C000 – 2000 DFFF S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF yes
yes 2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF yes
yes 2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF yes
yes 2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF yes
yes 2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF yes
yes 2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF yes
yes 2001 8000 – 2001 9FFF C4 RAM (Parity) 8K
yes 2001 A000 – 2001 BFFF C5 RAM (Parity) 8K
yes 2001 C000 – 2001 DFFF C6 RAM (Parity) 8K
yes 2001 E000 – 2001 FFFF C7 RAM (Parity) 8K
yes 2002 0000 – 2002 1FFF C8 RAM (Parity) 8K
yes 2002 2000 – 2002 3FFF C9 RAM (Parity) 8K
yes 2002 4000 – 2002 5FFF C10 RAM (Parity) 8K
yes 2002 6000 – 2002 7FFF C11 RAM (Parity) 8K
yes 2002 8000 – 2002 9FFF C12 RAM (Parity) 8K
yes 2002 A000 – 2002 BFFF C13 RAM (Parity) 8K
yes 2002 C000 – 2002 DFFF C14 RAM (Parity) 8K
yes 2002 E000 – 2002 FFFF C15 RAM (Parity) 8K
2003 0000 – 2007 EFFF Reserved
yes
read only
2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yes
yes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF yes
read only
no 2008 0000 – 2008 1FFF C0 RAM - ECC Bits 8K
no 2008 2000 – 2008 3FFF C1 RAM - ECC Bits 8K
no 2008 4000 – 2008 5FFF C2 RAM - Parity Bits 8K
no 2008 6000 – 2008 7FFF C3 RAM - Parity Bits 8K
no 2008 8000 – 2008 9FFF S0 RAM - Parity Bits 8K 0004 C000 – 0004 CFFF no
no 2008 A000 – 2008 BFFF S1 RAM - Parity Bits 8K 0004 D000 – 0004 DFFF no
no 2008 C000 – 2008 DFFF S2 RAM - Parity Bits 8K 0004 E000 – 0004 EFFF no
no 2008 E000 – 2008 FFFF S3 RAM - Parity Bits 8K 0004 F000 – 0004 FFFF no
no 2009 0000 – 2009 1FFF S4 RAM - Parity Bits 8K 0005 0000 – 0005 0FFF no
no 2009 2000 – 2009 3FFF S5 RAM - Parity Bits 8K 0005 1000 – 0005 1FFF no
no 2009 4000 – 2009 5FFF S6 RAM - Parity Bits 8K 0005 2000 – 0005 2FFF no
no 2009 6000 – 2009 7FFF S7 RAM - Parity Bits 8K 0005 3000 – 0005 3FFF no
no 2009 8000 – 2009 9FFF C4 RAM - Parity Bits 8K
no 2009 A000 – 2009 BFFF C5 RAM - Parity Bits 8K
no 2009 C000 – 2009 DFFF C6 RAM - Parity Bits 8K
no 2009 E000 – 2009 FFFF C7 RAM - Parity Bits 8K
no 200A 0000 – 200A 1FFF C8 RAM - Parity Bits 8K
no 200A 2000 – 200A 3FFF C9 RAM - Parity Bits 8K
no 200A 4000 – 200A 5FFF C10 RAM - Parity Bits 8K
no 200A 6000 – 200A 7FFF C11 RAM - Parity Bits 8K
no 200A 8000 – 200A 9FFF C12 RAM - Parity Bits 8K
no 200A A000 – 200A BFFF C13 RAM - Parity Bits 8K
no 200A C000 – 200A DFFF C14 RAM - Parity Bits 8K
no 200A E000 – 200A FFFF C15 RAM - Parity Bits 8K
200B 0000 – 200F EFFF Reserved
no 200F F000 – 200F F7FF CtoM MSG RAM - Parity Bits 2K 0007 F800 – 0007 FBFF no
no 200F F800 – 200F FFFF MtoC MSG RAM - Parity Bits 2K 0007 FC00 – 0007 FFFF no
2010 0000 – 21FF FFFF Reserved
yes 2200 0000 – 23FF FFFF Bit Banded RAM Zone
(Dedicated address for each RAM bit of Cortex-M3 RAM blocks above)
32M
yes 2400 0000 – 27FF FFFF All RAM Spaces – Mirror-Mapped for µCRC.
Accessing this memory by the µCRC peripheral will cause an access to
2000 0000 – 23FF FFFF memory space.
(Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register when reading a block of data.)
64M
2800 0000 – 3FFF FFFF Reserved
The letter "M" refers to the Master Subsystem.
The letter "C" refers to the Control Subsystem.

Table 6-10 Master Subsystem Peripherals

µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)
MASTER SUBSYSTEM PERIPHERALS SIZE
(BYTES)
C ADDRESS
(x16 ALIGNED)(2)
C DMA ACCESS(2)
yes 4000 0000 – 4000 0FFF Watchdog Timer 0 Registers 4K
yes 4000 1000 – 4000 1FFF Watchdog Timer 1 Registers 4K
4000 2000 – 4000 3FFF Reserved
yes 4000 4000 – 4000 4FFF M GPIO Port A (APB Bus)(1) 4K
yes 4000 5000 – 4000 5FFF M GPIO Port B (APB Bus)(1) 4K
yes 4000 6000 – 4000 6FFF M GPIO Port C (APB Bus)(1) 4K
yes 4000 7000 – 4000 7FFF M GPIO Port D (APB Bus)(1) 4K
yes 4000 8000 – 4000 8FFF SSI0 4K
yes 4000 9000 – 4000 9FFF SSI1 4K
yes 4000 A000 – 4000 AFFF SSI2 4K
yes 4000 B000 – 4000 BFFF SSI3 4K
yes 4000 C000 – 4000 CFFF UART0 4K
yes 4000 D000 – 4000 DFFF UART1 4K
yes 4000 E000 – 4000 EFFF UART2 4K
yes 4000 F000 – 4000 FFFF UART3 4K
yes 4001 0000 – 4001 0FFF UART4 4K
4001 1000 – 4001 FFFF Reserved
no 4002 0000 – 4002 07FF I2C0 Master 2K
no 4002 0800 – 4002 0FFF I2C0 Slave 2K
no 4002 1000 – 4002 17FF I2C1 Master 2K
no 4002 1800 – 4002 1FFF I2C1 Slave 2K
4002 2000 – 4002 3FFF Reserved
yes 4002 4000 – 4002 4FFF M GPIO Port E (APB Bus)(1) 4K
yes 4002 5000 – 4002 5FFF M GPIO Port F (APB Bus)(1) 4K
yes 4002 6000 – 4002 6FFF M GPIO Port G (APB Bus)(1) 4K
yes 4002 7000 – 4002 7FFF M GPIO Port H (APB Bus)(1) 4K
4002 8000 – 4002 FFFF Reserved
yes 4003 0000 – 4003 0FFF GP Timer 0 4K
yes 4003 1000 – 4003 1FFF GP Timer 1 4K
yes 4003 2000 – 4003 2FFF GP Timer 2 4K
yes 4003 3000 – 4003 3FFF GP Timer 3 4K
4003 4000 – 4003 CFFF Reserved
yes 4003 D000 – 4003 DFFF M GPIO Port J (APB Bus)(1) 4K
4003 E000 – 4003 FFFF Reserved
yes 4004 8000 – 4004 8FFF ENET MAC0 4K
4004 9000 – 4004 FFFF Reserved
yes 4005 0000 – 4005 0FFF USB MAC0 4K
4005 1000 – 4005 7FFF Reserved
yes 4005 8000 – 4005 8FFF M GPIO Port A (AHB Bus)(1) 4K
yes 4005 9000 – 4005 9FFF M GPIO Port B (AHB Bus)(1) 4K
yes 4005 A000 – 4005 AFFF M GPIO Port C (AHB Bus)(1) 4K
yes 4005 B000 – 4005 BFFF M GPIO Port D (AHB Bus)(1) 4K
yes 4005 C000 – 4005 CFFF M GPIO Port E (AHB Bus)(1) 4K
yes 4005 D000 – 4005 DFFF M GPIO Port F (AHB Bus)(1) 4K
yes 4005 E000 – 4005 EFFF M GPIO Port G (AHB Bus)(1) 4K
yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus)(1) 4K
yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus)(1) 4K
yes 4006 1000 – 4006 1FFF M GPIO Port K (AHB Bus)(1) 4K
yes 4006 2000 – 4006 2FFF M GPIO Port L (AHB Bus)(1) 4K
yes 4006 3000 – 4006 3FFF M GPIO Port M (AHB Bus)(1) 4K
yes 4006 4000 – 4006 4FFF M GPIO Port N (AHB Bus)(1) 4K
yes 4006 5000 – 4006 5FFF M GPIO Port P (AHB Bus)(1) 4K
yes 4006 6000 – 4006 6FFF M GPIO Port Q (AHB Bus)(1) 4K
yes 4006 7000 – 4006 7FFF M GPIO Port R (AHB Bus)(1) 4K
yes 4006 8000 – 4006 8FFF M GPIO Port S (AHB Bus)(1) 4K
4006 9000 – 4006 FFFF Reserved
no 4007 0000 – 4007 3FFF CAN0 16K
no 4007 4000 – 4007 7FFF CAN1 16K
4007 8000 – 400C FFFF Reserved
no 400D 0000 – 400D 0FFF EPI0 (Registers only) 4K
400D 1000 – 400F 9FFF Reserved
no 400F A000 – 400F A303 M Flash Control Registers(1) 772
400F A304 – 400F A5FF Reserved
no 400F A600 – 400F A647 M Flash ECC Error Log Registers(1) 72
400F A648 – 400F AFFF Reserved
no 400F B000 – 400F B1FF Reserved
no 400F B200 – 400F B2FF RAM Configuration Registers 256 0000 4900 – 0000 497F no
no 400F B300 – 400F B3FF RAM ECC/Parity/Access Error Log Registers 256 0000 4A00 – 0000 4A7F no
no 400F B400 – 400F B5FF M CSM Registers(1) 512
no 400F B600 – 400F B67F µCRC 128
400F B680 – 400F B6FF Reserved
no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 128 0000 4E00 – 0000 4E3F no
400F B780 – 400F B7FF Reserved
no 400F B800 – 400F B87F M Clock Control Registers(1) 128 0000 4400 – 0000 443F no
no 400F B880 – 400F B8BF M LPM Control Registers(1) 64
no 400F B8C0 – 400F B8FF M Reset Control Registers(1) 64
no 400F B900 – 400F B93F Device Configuration Registers 64 0000 0880 – 0000 0890 (Read Only)
400F B940 – 400F B97F Reserved
no 400F B980 – 400F B9FF M Write Protect Registers(1) 128
no 400F BA00 – 400F BA7F M NMI Registers(1) 128
400F BA80 – 400F BAFF Reserved
no 400F BB00 – 400F BBFF Reserved
400F BC00 – 400F EFFF Reserved
no 400F F000 – 400F FFFF µDMA Registers 4K
4010 0000 – 41FF FFFF Reserved
yes 4200 0000 – 43FF FFFF Bit Banded Peripheral Zone
(Dedicated address for each register bit of Cortex-M3 peripherals above.)
32M
4400 0000 – 4FFF FFFF Reserved
The letter "M" refers to the Master Subsystem.
The letter "C" refers to the Control Subsystem.

Table 6-11 Master Subsystem Analog and EPI

µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)
MASTER SUBSYSTEM
ANALOG AND EPI
SIZE
(BYTES)
C ADDRESS
(x16 ALIGNED)(2)
C DMA ACCESS(2)
5000 0000 – 5000 15FF Reserved
yes 5000 1600 – 5000 161F ADC1 Result Registers 32
5000 1620 – 5000 167F Reserved
yes 5000 1680 – 5000 169F ADC2 Result Registers 32
5000 16A0 – 5FFF FFFF Reserved
yes 6000 0000 – DFFF FFFF EPI0
(External Peripheral/Memory Interface)
2G 0030 0000 – 003F 7FFF(3) yes
The letter "M" refers to the Master Subsystem.
The letter "C" refers to the Control Subsystem.
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.

Table 6-12 Cortex-M3 Private Bus

µDMA ACCESS Cortex-M3 ADDRESS
(BYTE-ALIGNED)
Cortex-M3 PRIVATE BUS SIZE
(BYTES)
no E000 0000 – E000 0FFF ITM (Instrumentation Trace Macrocell) 4K
no E000 1000 – E000 1FFF DWT (Data Watchpoint and Trace) 4K
no E000 2000 – E000 2FFF FPB (Flash Patch and Breakpoint) 4K
E000 3000 – E000 E007 Reserved
no E000 E008 – E000 E00F System Control Block 8
no E000 E010 – E000 E01F System Timer 16
E000 E020 – E000 E0FF Reserved
no E000 E100 – E000 E4EF Nested Vectored Interrupt Controller (NVIC) 1008
E000 E4F0 – E000 ECFF Reserved
no E000 ED00 – E000 ED3F System Control Block 64
E000 ED40 – E000 ED8F Reserved
no E000 ED90 – E000 EDB8 Memory Protection Unit 41
E000 EDB9 – E000 EEFF Reserved
no E000 EF00 – E000 EF03 Nested Vectored Interrupt Controller 4
E000 EF04 – FFFF FFFF Reserved

Identification

Table 6-13 Device Identification Registers

NAME C ADDRESS
(x16 ALIGNED)(1)
M ADDRESS
(BYTE ALIGNED)(2)
DESCRIPTION
DID0.REVID 400F E000 – 400F E001 Device Identification 0 Register - Revision_ID
REVID 0x0000 0883 REVID - Current Revision ID of device
Silicon Revision Number REVID
0 0x0000
A 0x0001
B 0x0001
E 0x0005
F 0x0005
DID1.PARTNO 400F E006 Device Identification 1 Register - Part_Number
PARTID.PARTNO 0x0000 0882 C28x Device PARTID Register - Device Part Number
Device PARTNO (M3/C28x)
F28M36P63C2 0xFF
F28M36P53C2 0xFA
F28M36H53C2  0xEE
F28M36H53B2 0xEC
F28M36H33C2 0xEA
F28M36H33B2 0xE8
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.

Master Subsystem

The Master Subsystem includes the Cortex-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC), Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and read ADC Result Registers through the Analog Common Interface Bus. The Master Subsystem can also receive events from the NMI block and send events to the Resets block.

Figure 6-1 shows the Master Subsystem.

Cortex-M3 CPU

The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus cycles from both the Cortex-M3 System Bus and those of the µDMA bus to access the Master Subsystem peripherals (through the APB bus or the AHP bus).

Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex-M3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not properly serviced.

The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 m3_subsys_prs820.gif Figure 6-1 Master Subsystem

Cortex-M3 DMA and NVIC

The Cortex-M3 direct memory access (µDMA) module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the Cortex-M3 CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU.

The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the Cortex-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral, REQ/DONE will directly drive IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing the DMA. This case is true for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the µDMA or the NVIC (only to the Resets block).

Cortex-M3 Interrupts

Table 6-14 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 6-15.

Table 6-14 Interrupts from NVIC to Cortex-M3

INTERRUPT NUMBER
(BIT IN INTERRUPT REGISTERS)
VECTOR NUMBER VECTOR ADDRESS OR OFFSET DESCRIPTION
0–15 0x0000.0000–0x0000.003C Processor exceptions
0 16 0x0000.0040 GPIO Port A
1 17 0x0000.0044 GPIO Port B
2 18 0x0000.0048 GPIO Port C
3 19 0x0000.004C GPIO Port D
4 20 0x0000.0050 GPIO Port E
5 21 0x0000.0054 UART0
6 22 0x0000.0058 UART1
7 23 0x0000.005C SSI0
8 24 0x0000.0060 I2C0
9–17 25–33 Reserved
18 34 0x0000.0088 Watchdog Timers 0 and 1
19 35 0x0000.008C Timer 0A
20 36 0x0000.0090 Timer 0B
21 37 0x0000.0094 Timer 1A
22 38 0x0000.0098 Timer 1B
23 39 0x0000.009C Timer 2A
24 40 0x0000.00A0 Timer 2B
25–27 41–43 Reserved
28 44 0x0000.00B0 System Control
29 45 Reserved
30 46 0x0000.00B8 GPIO Port F
31 47 0x0000.00BC GPIO Port G
32 48 0x0000.00C0 GPIO Port H
33 49 0x0000.00C4 UART2
34 50 0x0000.00C8 SSI1
35 51 0x0000.00CC Timer 3A
36 52 0x0000.00D0 Timer 3B
37 53 0x0000.00D4 I2C1
38–41 54–57 Reserved
42 58 0x0000.00E8 Ethernet Controller
44 60 0x0000.00F0 USB
45 61 Reserved
46 62 0x0000.00F8 µDMA Software
47 63 0x0000.00FC µDMA Error
48–52 64–68 Reserved
53 69 0x0000.0114 EPI
54 70 0x0000.0118 GPIO Port J
55 71 0x0000.011C GPIO Port K
56 72 0x0000.0120 GPIO Port L
57 73 0x0000.0124 SSI 2
58 74 0x0000.0128 SSI 3
59 75 0x0000.012C UART3
60 76 0x0000.0130 UART4
61–63 77–79 Reserved
64 80 0x0000.0140 CAN0 INT0
65 81 0x0000.0144 CAN0 INT1
66 82 0x0000.0148 CAN1 INT0
67 83 0x0000.014C CAN1 INT1
68–71 84–87 Reserved
72 88 0x0000.0160 ADCINT1
73 89 0x0000.0164 ADCINT2
74 90 0x0000.0168 ADCINT3
75 91 0x0000.016C ADCINT4
76 92 0x0000.0170 ADCINT5
77 93 0x0000.0174 ADCINT6
78 94 0x0000.0178 ADCINT7
79 95 0x0000.017C ADCINT8
80 96 0x0000.0180 CTOMIPC1
81 97 0x0000.0184 CTOMIPC2
82 98 0x0000.0188 CTOMIPC3
83 99 0x0000.018C CTOMIPC4
84–87 100–103 Reserved
88 104 0x0000.01A0 RAM Single Error
89 105 0x0000.01A4 System / USB PLL Out of Lock
90 106 0x0000.01A8 M3 Flash Single Error
91 107 0x0000.01AC Reserved
92–110 108–126 Reserved
111 127 0x0000.01FC GPIO Port M
112 128 0x0000.0200 GPIO Port N
113–115 129–131 Reserved
116 132 0x0000.0210 GPIO Port P
117–123 133–139 Reserved
124 140 0x0000.0230 GPIO Port Q
125–131 141–147 Reserved
132 148 0x0000.0250 GPIO Port R
133 149 0x0000.0254 GPIO Port S

Table 6-15 Exceptions from Cortex-M3 Core to NVIC

EXCEPTION TYPE PRIORITY(1) VECTOR NUMBER VECTOR ADDRESS OR OFFSET ACTIVATION
0 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset.
Reset –3 (highest) 1 0x0000.0004 Asynchronous
Nonmaskable Interrupt (NMI) –2 2 0x0000.0008 Asynchronous
On Concerto devices activated by clock fail condition, C28 PIE error, external M3GPIO NMI input signal, and C28 NMI WD time-out reset.
Hard Fault –1 3 0x0000.000C
Memory Management programmable 4 0x0000.0010 Synchronous
Bus Fault programmable 5 0x0000.0014 Synchronous when precise and asynchronous when imprecise.
On Concerto devices activated by memory access errors and RAM and flash uncorrectable data errors.
Usage Fault programmable 6 0x0000.0018 Synchronous
7–10 Reserved
SVCall programmable 11 0x0000.002C Synchronous
Debug Monitor programmable 12 0x0000.0030 Synchronous
13 Reserved
PendSV programmable 14 0x0000.0038 Asynchronous
SysTick programmable 15 0x0000.003C Asynchronous
Interrupts programmable 16 and above 0x0000.0040 and above Asynchronous
0 is the default priority for all the programmable priorities

Cortex-M3 Vector Table

Each peripheral interrupt of Table 6-14 is assigned an address offset containing the location of the peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 16–107).

Similarly, each exception interrupt of Table 6-15 (including Reset) is also assigned an address offset containing the location of the exception interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 1–15).

In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table location 0.

Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000 0200 to 0x3FFF FE00. When configuring the VTABLE register, the offset must be aligned on a 512-byte boundary.

Cortex-M3 Local Peripherals

The Cortex-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB + PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus (Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem. The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and AHB bus cycles originate from the CPU System Bus or the µDMA Bus through a bus bridge.

While the Cortex-M3 CPU has access to all the peripherals, the µDMA has access to most, with the exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The Cortex-M3 peripherals connect to the Concerto device pins through GPIO_MUX1. Most of the peripherals also generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets block.

See Section 5.11 for more information on the Cortex-M3 peripherals.

Cortex-M3 Local Memory

The Local Memory includes Boot ROM; Secure Flash with ECC; Secure C0/C1 RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the Cortex-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex-M3 CPU; the C2/C3 RAM is also accessible by the µDMA.

Two types of error correction events can be generated during access of the Local Memory: uncorrectable errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a Bus Fault Exception to the Cortex-M3 CPU. The less critical single errors go to the NVIC where they can result in maskable interrupts to the Cortex-M3 CPU.

Cortex-M3 Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.

The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity Error Checking.

The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and µDMA. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.

The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling).

The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem.

The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations in both the Master Subsystem and the Control Subsystem.

See Section 5.10 for more information on shared resources and analog peripherals.

Control Subsystem

The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block, DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals through the Analog Common Interface Bus.

Figure 6-2 shows the Control Subsystem.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 c28x_subsys_prs820.gif Figure 6-2 Control Subsystem

C28x CPU/FPU/VCU

The F28M36x Concerto MCU family is a member of the TMS320C2000 MCU platform. The Concerto C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Piccolo MCUs, combined with a single-precision (32-bit) IEEE 754 FPU of TI’s existing Delfino MCUs. Each F28M36x device is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. Each F28M36x device also enables math algorithms to be developed using C/C++. The device is equally efficient at DSP math tasks and at system control tasks. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. With the addition of the fast interrupt response with automatic context save of critical registers, the device is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special conditional store operations further improve performance. The VCU extends the capabilities of the C28x CPU and C28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have been made to existing instructions, pipeline, or memory bus architecture. Therefore, programs written for the C28x are completely compatible with the C28x+VCU.

There are two events generated by the FPU block that go to the C28x PIE: LVF and LUV. Inside PIE, these and other events from C28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into the C28x CPU. The C28x CPU also receives three additional interrupts directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block (C28uNMIINT).

The C28x has two low-power modes: IDLE and STANDBY.

C28x Core Hardware Built-In Self-Test

The Concerto microcontroller C28x CPU core includes a HWBIST feature for testing the CPU core logic for errors. Tests using HWBIST can be initiated through a software library provided by TI.

C28x Peripheral Interrupt Expansion

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28M36x, 72 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block.

See Table 6-16 for PIE interrupt assignments.

Table 6-16 PIE Peripheral Interrupts(1)

CPU INTERRUPTS PIE INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1 C28.LPMWAKE
(C28LPM)
0x0D4E
TINT0
(TIMER 0)
0x0D4C
Reserved

0x0D4A
XINT2

0x0D48
XINT1

0x0D46
Reserved

0x0D44
ADCINT2
(ADC)
0x0D42
ADCINT1
(ADC)
0x0D40
INT2 EPWM8_TZINT
(ePWM8)
0x0D5E
EPWM7_TZINT
(ePWM7)
0x0D5C
EPWM6_TZINT
(ePWM6)
0x0D5A
EPWM5_TZINT
(ePWM5)
0x0D58
EPWM4_TZINT
(ePWM4)
0x0D56
EPWM3_TZINT
(ePWM3)
0x0D54
EPWM2_TZINT
(ePWM2)
0x0D52
EPWM1_TZINT
(ePWM1)
0x0D50
INT3 EPWM8_INT
(ePWM8)
0x0D6E
EPWM7_INT
(ePWM7)
0x0D6C
EPWM6_INT
(ePWM6)
0x0D6A
EPWM5_INT
(ePWM5)
0x0D68
EPWM4_INT
(ePWM4)
0x0D66
EPWM3_INT
(ePWM3)
0x0D64
EPWM2_INT
(ePWM2)
0x0D62
EPWM1_INT
(ePWM1)
0x0D60
INT4 EPWM9_TZINT
(ePWM9)
0x0D7E
EPWM10_TZINT
(ePWM10)
0x0D7C
ECAP6_INT
(eCAP6)
0x0D7A
ECAP5_INT
(eCAP5)
0x0D78
ECAP4_INT
(eCAP4)
0x0D76
ECAP3_INT
(eCAP3)
0x0D74
ECAP2_INT
(eCAP2)
0x0D72
ECAP1_INT
(eCAP1)
0x0D70
INT5 EPWM9_INT
(ePWM9)
0x0D8E
EPWM10_INT
(ePWM10)
0x0D8C
Reserved

0x0D8A
Reserved

0x0D88
Reserved

0x0D86
EQEP3_INT
(eQEP3)
0x0D84
EQEP2_INT
(eQEP2)
0x0D82
EQEP1_INT
(eQEP1)
0x0D80
INT6 EPWM11_TZINT
(ePWM11)
0x0D9E
EPWM12_TZINT
(ePWM12)
0x0D9C
MXINTA
(McBSPA)
0x0D9A
MRINTA
(McBSPA)
0x0D98
Reserved

0x0D96
Reserved

0x0D94
SPITXINTA
(SPIA)
0x0D92
SPIRXINTA
(SPIA)
0x0D90
INT7 EPWM11_INT
(ePWM11)
0x0DAE
EPWM12_INT
(ePWM12)
0x0DAC
DINTCH6
(C28 DMA)
0x0DAA
DINTCH5
(C28 DMA)
0x0DA8
DINTCH4
(C28 DMA)
0x0DA6
DINTCH3
(C28 DMA)
0x0DA4
DINTCH2
(C28 DMA)
0x0DA2
DINTCH1
(C28 DMA)
0x0DA0
INT8 Reserved

0x0DBE
Reserved

0x0DBC
Reserved

0x0DBA
Reserved

0x0DB8
Reserved

0x0DB6
Reserved

0x0DB4
I2CINT2A
(I2CA)
0x0DB2
I2CINT1A
(I2CA)
0x0DB0
INT9 Reserved

0x0DCE
Reserved

0x0DCC
Reserved

0x0DCA
Reserved

0x0DC8
Reserved

0x0DC6
Reserved

0x0DC4
SCITXINTA
(SCIA)
0x0DC2
SCIRXINTA
(SCIA)
0x0DC0
INT10 ADCINT8
(ADC)
0x0DDE
ADCINT7
(ADC)
0x0DDC
ADCINT6
(ADC)
0x0DDA
ADCINT5
(ADC)
0x0DD8
ADCINT4
(ADC)
0x0DD6
ADCINT3
(ADC)
0x0DD4
ADCINT2
(ADC)
0x0DD2
ADCINT1
(ADC)
0x0DD0
INT11 Reserved

0x0DEE
Reserved

0x0DEC
Reserved

0x0DEA
Reserved

0x0DE8
MTOCIPCINT4
(IPC)
0x0DE6 
MTOCIPCINT3
(IPC)
0x0DE4
MTOCIPCINT2
(IPC)
0x0DE2
MTOCIPCINT1
(IPC)
0x0DE0
INT12 LUF
(C28FPU)
0x0DFE
LVF
(C28FPU)
0x0DFC
EPI_INT
(EPI)
0x0DFA
C28RAMACCVIOL
(Memory)
0x0DF8
C28RAMSINGERR
(Memory)
0x0DF6
Reserved

0x0DF4
C28FLSINGERR
(Memory)
0x0DF2
XINT3
(Ext. Int. 3)
0x0DF0
Out of the 96 possible interrupts, 72 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).

C28x Direct Memory Access

The C28x DMA module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher priority than the others.

C28x Local Peripherals

The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2C), an EPI, and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are accessible by the C28x CPU through the C28x Memory Bus. Additionally, the McBSP and ePWM are accessible by the C28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The Serial Port Peripherals and the Control Peripherals connect to the pins in Concerto through the GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and the Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and sends a counter time-out event to the Cortex-M3 NMI block and the Resets block to flag a potentially critical condition.

The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1.

See Section 5.12 for more information on C28x peripherals.

C28x Local Memory

The C28x Local Memory includes Boot ROM; Secure Flash with ECC; Secure L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of error correction events can be generated during access of the C28x Local Memory: uncorrectable errors and single errors. The uncorrectable errors propagate to the NMI block where they can become the C28NMI to the C28x NMI Watchdog and the C28NMIINT nonmaskable interrupt to the C28x CPU. The less critical single errors go to the PIE block where they can become maskable interrupts to the C28x CPU.

C28x Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem.

The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks.

The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have Parity-Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.

The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling).

The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem.

See Section 5.10 for more information on shared resources and analog peripherals.

Analog Subsystem

The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex-M3 Subsystem. In addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem.

There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).

Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the C28x DMA.

The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with the two digital subsystems of Concerto (Cortex-M3 and C28x).

Figure 6-3 shows the Analog Subsystem.

ADC1

The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 12 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC1 result registers.

See Section 5.10.1 for more information on ADC peripherals.

ADC2

The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 12 are currently pinned out. The analog channels are internally preassigned to two S/H units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC2 result registers.

See Section 5.10.1 for more information on ADC peripherals.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 analog_subsys_prs820.gif Figure 6-3 Analog Subsystem

Analog Comparator + DAC

There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs, resulting in six digital comparison outputs. The external analog inputs that are being compared in the comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be mapped to six out of eight available pins.

To use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be assigned to selected 12 ePWM Trip Inputs.

See Section 5.10.2 for more information on the analog comparator + DAC.

Analog Common Interface Bus

The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the Cortex-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3 uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem side.

Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems. The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines because it is unlikely that any application would need all 16 interrupts at the same time.

Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22 possible trigger sources to each SOC trigger.

There are two registers that provide status of ACIB to the Master Subsystem and to the Control Subsystem.

The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems.

The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems.

Master Subsystem NMIs

The Cortex-M3 NMI Block generates an M3NMIINT nonmaskable interrupt to the Cortex-M3 CPU and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an M3NMIRST reset signal is sent to the Resets block.

The inputs to the Cortex-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR, EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the C28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected.

The Cortex-M3 NMI block can be accessed through the Cortex-M3 NMI configuration registers—including the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively.

Figure 6-4 shows the Cortex-M3 NMI and C28x NMI.

Control Subsystem NMIs

The C28x NMI Block generates a C28NMIINT nonmaskable interrupt to the C28x CPU and a C28NMI event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the C28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3 NMI Block can generate an NMI to the Cortex-M3 processor.

The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR, PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x PIE block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected.

The C28x NMI block can be accessed through the C28x NMI configuration registers—including the CNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively.

Figure 6-4 shows the Cortex-M3 NMI and C28x NMI.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 nmi_prs820.gif Figure 6-4 Cortex-M3 NMI and C28x NMI

Resets

The Concerto MCU has two external reset pins: XRS for the Master and Control Subsystems and ARS for the Analog Subsystem. Texas Instruments (TI) recommends that these two pins be externally tied together with a board signal trace.

The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control Subsystems. A reset pulse can also be driven out of the XRS pin by the Power-On Reset (POR) block of the Master and Control Subsystems (see Section 6.9). A reset pulse can be driven out of the XRS pin when the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog time-out.

There are some requirements on the XRS pin:

  1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is stable. This requirement is to enable the entire device to start from a known condition.
  2. TI recommends that no voltage larger than 0.7 V be applied to any pin before powering up the device. Voltages applied to pins on an unpowered device can lead to unpredictable results.

The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset pulse can be driven out of the ARS pin by the POR block of the Analog Subsystem.

Figure 6-5 shows the resets.

Cortex-M3 Resets

The Cortex-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR or the M3SYSRST reset signal. In both cases, the Cortex-M3 CPU restarts program execution from the address provided by the reset entry in the vector table. A register can later be referenced to determine the source of the reset. The M3SYSRST signal also propagates to the Cortex-M3 peripherals and the rest of the Cortex-M3 Subsystem.

The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS is set in response to time-out conditions of the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two resets also propagate to the C28x Subsystem and the Analog Subsystem.

The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from the Cortex-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface Bus. In addition to driving reset signals to other parts of the chip, the Cortex-M3 can also detect a C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS register.

Cortex-M3 software can also set bits in the SRCR register to selectively reset individual Cortex-M3 peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause register (MRESC) can be read to find out if the latest reset was caused by External Reset, POR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 resets_prs820.gif Figure 6-5 Resets

C28x Resets

The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the address provided at the top of the Boot ROM Vector Table.

The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to selectively reset the C28x Subsystem from Cortex-M3 software.

The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin by reading the DEVICECNF register.

Analog Subsystem and Shared Resources Resets

Both the Analog Subsystem and the resources shared between the C28x and Cortex-M3 subsystems (IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry.

The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the Analog Subsystem and the Shared Resources.

Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is reset by M3SYSRST.

Device Boot Sequence

The boot sequence of Concerto is used to configure the Master Subsystem and the Control Subsystem for execution of application code. The boot sequence involves both internal resources, and resources external to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex-M3 and C28x peripherals for loading the application code into the Master and Control Subsystems.

The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3 NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and then both bootloaders work in tandem to configure the device, load application code for both processors (if not already in the Flash), and branch the execution of each processor to a selected location in the application code.

Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem, the C-Bootloader enters the C28x processor into the IDLE mode (to wait for the M-Bootloader to wake up the C28x processor later through the MTOCIPC1 interrupt). Next, the M-Bootloader reads four GPIO pins (see Table 6-17) to determine the boot mode for the rest of the M-Bootloader operation.

Table 6-17 Master Subsystem Boot Mode Selection

BOOT MODE # MASTER SUBSYSTEM BOOT MODES PF2_GPIO34
(Bmode_pin4)(1)
PF3_GPIO35
(Bmode_pin3)(1)
PG7_GPIO47
(Bmode_pin2)(1)
PG3_GPIO43
(Bmode_pin1)(1)
0(2) Boot from Parallel GPIO 0 0 0 0
1(2) Boot to Master Subsystem RAM 0 0 0 1
2(2) Boot from Master Subsystem serial peripherals (UART0/SSI0/I2C0) 0 0 1 0
3(2) Boot from Master Subsystem CAN interface 0 0 1 1
4(2) Boot from Master Subsystem Ethernet interface 0 1 0 0
5(2)(4) Not supported (Defaults to Boot-to-Flash), future boot from Cortex-M3 USB 0 1 0 1
6(2)(4)(5) Boot-to-OTP 0 1 1 0
7(2)(4) Boot to Master Subsystem Flash memory 0 1 1 1
8 Not supported (Defaults to Boot-to-Flash) 1 0 0 0
9(4) Boot from Master Subsystem serial peripheral – SSI0 Master 1 0 0 1
10(4) Boot from Master Subsystem serial peripheral – I2C0 Master 1 0 1 0
11(4) Not supported (Defaults to Boot-to-Flash) 1 0 1 1
12(3) Boot from Master Subsystem Ethernet interface 1 1 0 0
13(4) Not supported (Defaults to Boot-to-Flash) 1 1 0 1
14(4) Not supported (Defaults to Boot-to-Flash) 1 1 1 0
15(4) Boot to Master Subsystem Flash memory 1 1 1 1
  1. By default, GPIO terminals are not pulled up (they are floating).
  2. Boot Modes 0–7 are pin-compatible with the F28M35x members of the Concerto family (they use same GPIO terminals).
  3. Boot Mode 12 is the same as Boot Mode 4, except it uses a different set of GPIO terminals.
  4. This Boot Mode uses a faster Flash power-up sequence. The maximum supported OSCCLK frequency for this mode is 30 MHz.
  5. Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash.

Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the Master Flash memory. This branching requires that the Master Flash be already programmed with valid code; otherwise, a hard fault exception is generated and the Cortex-M3 goes back to the above reset sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until the emulator is connected and a debug session started.) If the Master Subsystem Flash has already been programmed, the application code will start execution. Typically, the Master Subsystem application code will then establish data communication with the C28x [through the IPC (Interprocessor Communications peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Boot Mode 15 (Fast Boot to Flash Mode) supported on this device is a special boot to Flash mode, which configures Flash for a faster power up, thus saving some boot time. Boot Mode 7 and other modes which default to Flash do not configure Flash for a faster power up like Boot Mode 15 does. Following reset, the internal pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four external pullups.

Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3 processor starts executing code that has been preloaded earlier. Typically, this mode is used during development of application code meant for Flash, but which has to be first tested running out of RAM. In this case, the user would typically load the application code into RAM using the debugger, and then issue a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot process on the Master Subsystem side is controlled by the application code.

Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external peripheral before branching to the application code. This process is different from the process in Boot Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into RAM by the emulator. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins. If the boot pins are set to 0010b, the application code will be loaded from the Master Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the F28M35x device. If the boot pins are set to 1001b or 1010b, then the application code will be loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. If the boot pins are set to 1100b, then the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are F28M36x IOs, which are available only in a BGA package.

Regardless of the type of boot mode selected, once the Master application code is resident in Master Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the application code takes over control from the M-Bootloader, and the boot process continues as prescribed by the application code. At this stage, the Master application program typically establishes communication with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the C28x to go into IDLE mode. To wake the Control Subsystem out of IDLE mode, the Master application issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1) . Once the data communication has been established through the IPC, the boot process can now also continue on the Control Subsystem side.

The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to branch to preloaded code in RAM (development mode), or to upload the Control application code from one of several available peripherals (see Table 6-18). As before, once the Control application code is in place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the application code takes over.

Table 6-18 Control Subsystem Boot Mode Selection

CONTROL SUBSYSTEM
BOOT MODES
MTOCIPCBOOTMODE
REGISTER VALUE
DESCRIPTION
BOOT_FROM_RAM 0x0000 0001 Upon receiving this command from the Master Subsystem, C-Boot ROM will branch to the Control Subsystem RAM entry point location and start executing code from there.
BOOT_FROM_FLASH 0x0000 0002 Upon receiving this command, C-Boot ROM will branch to the Control Subsystem FLASH entry point and start executing code from there.
BOOT_FROM_SCI 0x0000 0003 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SCI peripheral.
BOOT_FROM_SPI 0x0000 0004 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SPI interface.
BOOT_FROM_I2C 0x0000 0005 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem I2C interface.
BOOT_FROM_PARALLEL 0x0000 0006 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem GPIO.
BOOT_FROM_SPI(1) 0x0000 0007 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SPI interface.
MTOCBOOTMODE 0x0000 0001–MTOCBOOTMODE 0x0000 0006 are compatible with the F28M35x members of the Concerto family, but MTOCBOOTMODE 0x0000 0007 uses GPIO terminals that are not available on the F28M35x.

The boot process can be considered completed once the Cortex-M3 and C28x are both running out of their respective application programs. Following the boot sequence, the C-Bootloader is still available to interpret and act upon an assortment of IPC commands that can be issued from the Master Subsystem to perform a variety of configuration, housekeeping, and other functions.

Internal Voltage Regulation and Power-On-Reset Functionality

While the analog functions of Concerto draw power from a single dedicated external power source—VDDA, its digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This section describes the sourcing, regulation, and POR functionality for these three digital power rails.

Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the Cortex-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses VDD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems share a common VDDIO rail to power their 3.3-V I/O buffers through which the Concerto digital signals communicate with the outside world.

The Analog and Digital Subsystems each have their own POR circuits that operate independently. With the ARS and XRS reset pins externally tied together, both systems can come out of reset together, and can also be put in reset together by driving both reset pins low. See Figure 6-6 for a snapshot of the voltage regulation and POR functions provided within the Analog and Digital Subsystems of Concerto.

Analog Subsystem: Internal 1.8-V VREG

The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8-V VREG provides 1.8 V to digital logic associated with the analog functions of the Analog Subsystem.

When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided externally; however, a 1.2-µF (10% tolerance) capacitor is required for each VDD18 pin to stabilize the internally generated voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is provided from an external supply.

While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power consumption.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 volt_reg_prs825.gif Figure 6-6 Voltage Regulation and Monitoring

Digital Subsystem: Internal 1.2-V VREG

The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic associated with the processors, memory, and peripherals of the Digital Subsystem.

When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided externally; however, the minimum and maximum capacitance required for each VDD12 pin to stabilize the internally generated voltages are 250 nF and 750 nF, respectively. These load capacitors are not required if the internal 1.2-V VREG is disabled and the 1.2 V is provided from an external supply.

While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power consumption.

Analog and Digital Subsystems: Power-On-Reset Functionality

The Analog and Digital Subsystems' each have a POR circuit that creates a clean reset throughout the device enabling glitchless GPIOs during the power-on procedure. The POR function keeps both ARS and XRS driven low during device power up. This functionality is always enabled, even when VREG is disabled.

While in most applications, the POR generated reset has a long enough duration to also reset other system ICs, some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset pins (which are open-drain) can also be driven low to match the time the device is held in a reset state with the rest of the system.

When POR drives the ARS and XRS pins low, the POR also resets the digital logic associated with both subsystems and puts the GPIO pins in a high impedance state.

In addition to the POR reset, the Resets block of the Digital Subsystem also receives reset inputs from the NVIC, the Cortex-M3 Watchdogs (0, 1), and from the Cortex-M3 NMI Watchdog. The resulting reset output signal is then fed back to the XRS pin after being AND-ed with the POR reset (see Figure 6-6).

On a related note, only the Master Subsystem comes out of reset immediately following a device power up. The Control and Analog Subsystems continue to be held in reset until the Master Processor (Cortex-M3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF Register (see Figure 6-6).

Connecting ARS and XRS Pins

In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external means such as through a signal trace on a PCB board. Tying the ARS and XRS pins together ensures that all reset sources will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where the reset condition occurs.

Input Clocks and PLLs

Concerto devices have multiple input clock pins from which all internal clocks and the output clock are derived. Figure 6-7 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 and XCLKIN.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 connecting_input_clocks_prs825.gif Figure 6-7 Connecting Input Clocks to a Concerto™ Device

Internal Oscillator (Zero-Pin)

Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency clocks: 10MHZCLK and 32KHZCLK. These clocks are not configurable by the user and should not be used to clock the device during normal operation. They are used inside the Master Subsystem to implement low-power modes. The 10MHZCLK is also used by the Missing Clock Detect circuit.

Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)

The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used (version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin VSSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors connected to the two crystal terminals as shown in Figure 6-7.

External Oscillators (Pins X1, VSSOSC, XCLKIN)

Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 6-7 shows how to connect external oscillators to the X1 and XCLKIN terminals.

Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer. Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the electromagnetic fields created by the two opposite currents cancel each other out as much as possible, thus reducing parasitic inductances that radiate EMI.

Main PLL

The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the Main PLL must be between 150 MHz and 300 MHz. The PLL output clock is then divided by 2 before entering a mux that selects between this clock and the PLL input clock – OSCCLK (used in PLL bypass mode). The PLL bypass mode is selected by setting the SPLLIMULT field of the SYSPLLMULT register to 0. The output clock from the mux next enters a divider controlled by the SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK. Figure 6-8 shows the Main PLL function and configuration examples. Table 6-19 to Table 6-22 list the integer multiplier configuration values.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 main_pll_prs825.gif Figure 6-8 Main PLL

Table 6-19 Main PLL Integer Multiplier Configuration
(Bypass PLL to × 31)

SPLLIMULT(6:0) MULT VALUE
0000000 b Bypass PLL
0000001 b × 1
0000010 b × 2
0000011 b × 3
0000100 b × 4
0000101 b × 5
0000110 b × 6
0000111 b × 7
 
0001000 b  × 8
0001001 b × 9
0001010 b × 10
0001011 b × 11
0001100 b × 12
0001101 b × 13
0001110 b × 14
0001111 b × 15
 
0010000 b × 16
0010001 b × 17
0010010 b × 18
0010011 b × 19
0010100 b × 20
0010101 b × 21
0010110 b × 22
0010111 b × 23
 
0011000 b × 24
0011001 b × 25
0011010 b × 26
0011011 b × 27
0011100 b × 28
0011101 b × 29
0011110 b × 30
0011111 b × 31

Table 6-20 Main PLL Integer Multiplier Configuration
(× 32 to × 63)

SPLLIMULT(6:0) MULT VALUE
0100000 b × 32
0100001 b × 33
0100010 b × 34
0100011 b × 35
0100100 b × 36
0100101 b × 37
0100110 b × 38
0100111 b × 39
 
0101000 b × 40
0101001 b × 41
0101010 b × 42
0101011 b × 43
0101100 b × 44
0101101 b × 45
0101110 b × 46
0101111 b × 47
 
0110000 b × 48
0110001 b × 49
0110010 b × 50
0110011 b × 51
0110100 b × 52
0110101 b × 53
0110110 b × 54
0110111 b × 55
 
0111000 b × 56
0111001 b × 57
0111010 b × 58
0111011 b × 59
0111100 b × 60
0111101 b × 61
0111110 b × 62
0111111 b × 63

Table 6-21 Main PLL Integer Multiplier Configuration
(× 64 to × 95)

SPLLIMULT(6:0) MULT VALUE
1000000 b × 64
1000001 b × 65
1000010 b × 66
1000011 b × 67
1000100 b × 68
1000101 b × 69
1000110 b × 70
1000111 b × 71
 
1001000 b × 72
1001001 b × 73
1001010 b × 74
1001011 b × 75
1001100 b × 76
1001101 b × 77
1001110 b × 78
1001111 b × 79
 
1010000 b × 80
1010001 b × 81
1010010 b × 82
1010011 b × 83
1010100 b × 84
1010101 b × 85
1010110 b × 86
1010111 b × 87
 
1011000 b × 88
1011001 b × 89
1011010 b × 90
1011011 b × 91
1011100 b × 92
1011101 b × 93
1011110 b × 94
1011111 b × 95

Table 6-22 Main PLL Integer Multiplier Configuration
(× 96 to × 127)

SPLLIMULT(6:0) MULT VALUE
1100000 b × 96
1100001 b × 97
1100010 b × 98
1100011 b × 99
1100100 b × 100
1100101 b × 101
1100110 b × 102
1100111 b × 103
 
1101000 b × 104
1101001 b × 105
1101010 b × 106
1101011 b × 107
1101100 b × 108
1101101 b × 109
1101110 b × 110
1101111 b × 111
 
1110000 b × 112
1110001 b × 113
1110010 b × 114
1110011 b × 115
1110100 b × 116
1110101 b × 117
1110110 b × 118
1110111 b × 119
 
1111000 b × 120
1111001 b × 121
1111010 b × 122
1111011 b × 123
1111100 b × 124
1111101 b × 125
1111110 b × 126
1111111 b × 127

USB PLL

The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the internal OSCCLK (originating from the external crystal or oscillator through the X1/X2 pins). An input mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 6-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider). Figure 6-9 shows the USB PLL function and configuration examples. Table 6-23 and Table 6-24 list the integer multiplier configuration values.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 usb_pll_prs825.gif Figure 6-9 USB PLL

Table 6-23 USB PLL Integer Multiplier Configuration
(Bypass PLL to × 31)

SPLLIMULT(5:0) MULT VALUE
000000 b Bypass PLL
000001 b × 1
000010 b × 2
000011 b × 3
000100 b × 4
000101 b × 5
000110 b × 6
000111 b × 7
 
001000 b × 8
001001 b × 9
001010 b × 10
001011 b × 11
001100 b × 12
001101 b × 13
001110 b × 14
001111 b × 15
 
010000 b × 16
010001 b × 17
010010 b × 18
010011 b × 19
010100 b × 20
010101 b × 21
010110 b × 22
010111 b × 23
 
011000 b × 24
011001 b × 25
011010 b × 26
011011 b × 27
011100 b × 28
011101 b × 29
011110 b × 30
011111 b × 31

Table 6-24 USB PLL Integer Multiplier Configuration
(× 32 to × 63)

SPLLIMULT(5:0) MULT VALUE
100000 b × 32
100001 b × 33
100010 b × 34
100011 b × 35
100100 b × 36
100101 b × 37
100110 b × 38
100111 b × 39
 
101000 b × 40
101001 b × 41
101010 b × 42
101011 b × 43
101100 b × 44
101101 b × 45
101110 b × 46
101111 b × 47
 
110000 b × 48
110001 b × 49
110010 b × 50
110011 b × 51
110100 b × 52
110101 b × 53
110110 b × 54
110111 b × 55
 
111000 b × 56
111001 b × 57
111010 b × 58
111011 b × 59
111100 b × 60
111101 b × 61
111110 b × 62
111111 b × 63

Master Subsystem Clocking

The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register.

There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The 10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this signal can trip the ePWM peripherals.

The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources for the Deep Sleep Clock.

There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.

The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 6-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals. Figure 6-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes.

Table 6-25 Master Subsystem Low-Power Modes

Cortex-M3
LOW-POWER MODE
STATE OF
Cortex-M3 CPU
CLOCK TO
Cortex-M3 PERIPHERALS
REGISTER USED TO GATE CLOCKS TO Cortex-M3 PERIPHERALS MAIN PLL USB PLL CLOCK TO C28x CLOCK TO SHARED RESOURCES CLOCK TO ANALOG SUBSYSTEM
Run Active M3SSCLK(1) RCGC On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3)
Sleep Stopped M3SSCLK(1) RCGC or SCGC(4) On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3)
Deep Sleep Stopped M3DSDIVCLK(5) RCGC or DCGC(4) Off Off Off Off Off
PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes 10MHZCLK divided-down per the M3SSDIVSEL register.
PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK.
Depends on the ACG bit of the RCC register.
32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL register (source determined inside the DSLPCLKCFG register).

Figure 6-11 shows the system clock/PLL.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 m3_clocks_prs825.gif Figure 6-10 Cortex-M3 Clocks and Low-Power Modes
F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 SYSCLK_PLL_prs742.gif Figure 6-11 System Clock/PLL

Cortex-M3 Run Mode

In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is accomplished through corresponding peripheral configuration registers. Clock gating for individual peripherals is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC (Device Configuration) register.

Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and forces the Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of the SLEEPDEEP bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3 processor/subsystem to Run Mode.

Cortex-M3 Sleep Mode

In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode.

Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter).

Cortex-M3 Deep Sleep Mode

In Deep Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking and thus the code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a corresponding DC register.

Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If 32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates OSCCLK) is turned off.

The Cortex-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is already in the STANDBY mode. Typically, just before entering the STANDBY mode, the C28x will record in the CLPMSTAT that it is about to do so. The Cortex-M3 processor can read the CLPMSTAT register to check if the C28x is in STANDBY mode, and only then should the Cortex-M3 processor go into Deep Sleep. The reason for the Cortex-M3 processor to confirm that the C28x is in STANDBY mode before the Cortex-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to C28x and its peripherals, and if this clock shutdown is not expected by the C28x, unintended consequences could result for some of the C28x control peripherals.

Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Deep Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter).

Control Subsystem Clocking

The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1 external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.

Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is done through the CPCLKCR0,2,3 registers.

The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by OSCCLK or 10MHZCLK (see Figure 6-12). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and PIE.

The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode. Table 6-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and peripherals. Figure 6-12 shows the Control Subsystem clocks and low-power modes.

Table 6-26 Control Subsystem Low-Power Modes(1)

C28x
LOW-POWER MODE
STATE OF C28x CPU C28CPUCLK(2) C28SYSCLK(3) REGISTERS USED TO GATE CLOCKS TO
C28x PERIPHERALS
Normal Active On On CPCLKCR0,1,3
IDLE Stopped Off On CPCLKCR0,1,3
STANDBY Stopped Off Off N/A
The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem enters the Deep Sleep mode.
C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE.
C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.

C28x Normal Mode

In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK, OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals.

Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode or STANDBY Mode.

C28x IDLE Mode

In IDLE Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the C28NMIINT (C28x nonmaskable interrupt).

Upon exit from IDLE Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the IDLE Mode.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 c28x_clocks_prs820.gif Figure 6-12 C28x Clocks and Low-Power Modes

C28x STANDBY Mode

In STANDBY Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and C28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by one of 64 GPIOs from the GPIO_MUX1 block, or MTOCIPCINT2 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the CPCLKCR0 register) before propagating into the wake request logic.

Cortex-M3 should use CLPMSTAT register bits to tell the C28x to go into STANDBY mode before going into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control software is not expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wake-up should happen only from the Master Subsystem, because all C28x clocks are off (C28CLKIN, C28CPUCLK, C28SYSCLK), thus preventing the C28x from waking up first.

Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the STANDBY Mode.

NOTE

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not available).

Analog Subsystem Clocking

The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of ASYSCLK, it is possible for the Cortex-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem.

The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode.

Shared Resources Clocking

The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.

Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is clocked by M3SSCLK.

Loss of Input Clock (NMI Watchdog Function)

The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to enable other chip components to take corrective or recovery action from such event (see Figure 6-13).

The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator) so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK. Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a corresponding CPU, while starting the associated NMI watchdog counter.

If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in the device reset. If the software does react to the NMI, the software can prevent the impending reset by disabling the watchdog timers, and then the software can initiate necessary corrective action such as switching over to an alternative clock source (if available) or the software can initiate a shut-down procedure for the system.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 missing_clock_detect_prs825.gif Figure 6-13 Missing Clock Detection

GPIOs and Other Pins

Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished through several I/O muxes where a specific physical pin can be assigned to selected signals of internal peripherals.

Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN internal voltage regulator enables; and five JTAG pins. The 144 primary GPIOs are grouped in 2 programmable blocks: GPIO_MUX1 block (136 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 6-14 shows the GPIOs and other pins.

GPIO_MUX1

One-hundred and thirty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all Cortex-M3 peripherals, to all C28x peripherals, to 136 General-Purpose Inputs, to 136 General-Purpose Outputs, or a mixture of all of the above. The first 64 pins of GPIO_MUX1 (GPIO0–GPIO63) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the C28x PIE, and the C28x STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex-M3 peripherals (and not to C28x peripherals).

Figure 6-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the configuration registers are programmed in the blue and green blocks (see Figure 6-16 for the configuration registers).

Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to the 136 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[S:A] IRQ signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The 17 GPIO[S:A] IRQ signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can be selected to wake up the C28x CPU from Low-Power Mode. One-hundred and thirty-six (136) GPI signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see Figure 6-16).

The configuration registers for the muxing of Master Subsystem peripherals are organized in 17 sets (A–S), with each set being responsible for eight pins. The first nine sets of these registers (A–J) are programmable by the Cortex-M3 CPU through the AHB bus or the APB bus. The remaining sets of registers (K–S) are programmable by the AHB bus only. The configuration register for the muxing of Control Subsystem peripherals are organized in five sets (A–E), with each set being responsible for up to 32 pins. These registers are programmable by the C28x CPU through the C28x CPU bus. Figure 6-16 shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one GPIO pin as driven by these registers.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 gpio_prs820.gif Figure 6-14 GPIOs and Other Pins
F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 gpio_mux1_all_pins_prs820.gif Figure 6-15 GPIO_MUX1 Block
F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 gpio_mux1_one_pin_prs820.gif Figure 6-16 GPIO_MUX1 Pin Mapping Through Register Set A

For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of 11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input takes the reverse path. See Table 6-27 and Table 6-28 for the mapping of Cortex-M3 peripheral signals to GPIO_MUX1 pins.

Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along the muxing chain towards a given pin. The input takes the reverse path. See Table 6-29 for the mapping of C28x peripheral signals to GPIO_MUX1 pins.

In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital GPIO_MUX1 options as described above.

Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always available at these modules where it can be selected through local registers.

NOTE

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not available).

Table 6-27 GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1)

ANALOG
MODE
(USB PINS)
DEVICE
PIN NAME
M3
PRIMARY
MODE 1
M3
PRIMARY
MODE 2
M3
PRIMARY
MODE 3
M3
PRIMARY
MODE 4
M3
PRIMARY
MODE 5
M3
PRIMARY
MODE 6
M3
PRIMARY
MODE 7
M3
PRIMARY
MODE 8
M3
PRIMARY
MODE 9
M3
PRIMARY
MODE 10
M3
PRIMARY
MODE 11
PA0_GPIO0 U0RX I2C1SCL U1RX
PA1_GPIO1 U0TX I2C1SDA U1TX
PA2_GPIO2 SSI0CLK MIITXD2
PA3_GPIO3 SSI0FSS MIITXD1
PA4_GPIO4 SSI0RX MIITXD0 CAN0RX
PA5_GPIO5 SSI0TX MIIRXDV CAN0TX
PA6_GPIO6 I2C1SCL CCP1 MIIRXCK CAN0RX USB0EPEN
PA7_GPIO7 I2C1SDA CCP4 MIIRXER CAN0TX CCP3 USB0PFLT
PB0_GPIO8 CCP0 U1RX
PB1_GPIO9 CCP2 CCP1 U1TX
PB2_GPIO10 I2C0SCL CCP3 CCP0 USB0EPEN
PB3_GPIO11 I2C0SDA USB0PFLT
PB4_GPIO12 U2RX CAN0RX U1RX EPI0S23
PB5_GPIO13 CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22
PB6_GPIO14 CCP1 CCP7 CCP5 EPI0S37(2)
PB7_GPIO15 EXTNMI MIIRXD1 EPI0S36(2)
PD0_GPIO16 CAN0RX U2RX U1RX CCP6 MIIRXDV
PD1_GPIO17 CAN0TX U2TX U1TX CCP7 MIITXER CCP2
PD2_GPIO18 U1RX CCP6 CCP5 EPI0S20
PD3_GPIO19 U1TX CCP7 CCP0 EPI0S21
PD4_GPIO20 CCP0 CCP3 MIITXD3 EPI0S19
PD5_GPIO21 CCP2 CCP4 MIITXD2 U2RX EPI0S28
PD6_GPIO22 MIITXD1 U2TX EPI0S29
PD7_GPIO23 CCP1 MIITXD0 EPI0S30
PE0_GPIO24 SSI1CLK CCP3 EPI0S8 USB0PFLT
PE1_GPIO25 SSI1FSS CCP2 CCP6 EPI0S9
PE2_GPIO26 CCP4 SSI1RX CCP2 EPI0S24
PE3_GPIO27 CCP1 SSI1TX CCP7 EPI0S25
PE4_GPIO28 CCP3 U2TX CCP2 MIIRXD0 EPI0S34(2)
PE5_GPIO29 CCP5 EPI0S35(2)
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32 CAN1RX MIIRXCK
PF1_GPIO33 CAN1TX MIIRXER CCP3
PF2_GPIO34 MIIPHYINTR EPI0S32(2) SSI1CLK
PF3_GPIO35 MIIMDC EPI0S33(2) SSI1FSS
PF4_GPIO36 CCP0 MIIMDIO EPI0S12 SSI1RX
PF5_GPIO37 CCP2 MIIRXD3 EPI0S15 SSI1TX
USB0VBUS PF6_GPIO38 CCP1 MIIRXD2 EPI0S38(2)
PF7_GPIO39
PG0_GPIO40 U2RX I2C1SCL USB0EPEN EPI0S13
PG1_GPIO41 U2TX I2C1SDA EPI0S14
USB0DM PG2_GPIO42 MIICOL EPI0S39(2)
PG3_GPIO43 MIICRS
PG4_GPIO44
USB0DP PG5_GPIO45 CCP5 MIITXEN EPI0S40(2)
USB0ID PG6_GPIO46 MIITXCK EPI0S41(2)
PG7_GPIO47 MIITXER CCP5 EPI0S31
PH0_GPIO48 CCP6 MIIPHYRST EPI0S6
PH1_GPIO49 CCP7 EPI0S7
PH2_GPIO50 EPI0S1 MIITXD3
PH3_GPIO51 USB0EPEN EPI0S0 MIITXD2
PH4_GPIO52 USB0PFLT EPI0S10 MIITXD1 SSI1CLK
PH5_GPIO53 EPI0S11 MIITXD0 SSI1FSS
PH6_GPIO54 EPI0S26 MIIRXDV SSI1RX
PH7_GPIO55 MIIRXCK EPI0S27 SSI1TX
PJ0_GPIO56 MIIRXER EPI0S16 I2C1SCL
PJ1_GPIO57 EPI0S17 USB0PFLT I2C1SDA
PJ2_GPIO58 EPI0S18 CCP0
PJ3_GPIO59 EPI0S19 CCP6
PJ4_GPIO60 EPI0S28 CCP4
PJ5_GPIO61 EPI0S29 CCP2
PJ6_GPIO62 EPI0S30 CCP1
PJ7_GPIO63/
XCLKIN
CCP0
PC0_GPIO64 EPI0S32(2)
PC1_GPIO65 EPI0S33(2)
PC2_GPIO66 EPI0S37(2)
PC3_GPIO67 EPI0S36(2)
PC4_GPIO68 CCP5 MIITXD3 CCP2 CCP4 EPI0S2 CCP1
PC5_GPIO69 CCP1 CCP3 USB0EPEN EPI0S3
PC6_GPIO70 CCP3 U1RX CCP0 USB0PFLT EPI0S4
PC7_GPIO71 CCP4 CCP0 U1TX USB0PFLT EPI0S5
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.

Table 6-28 GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1)

ANALOG MODE
(USB PINS)
DEVICE PIN NAME M3
ALTERNATE
MODE 12
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
PA0_GPIO0
PA1_GPIO1 SSI1FSS
PA2_GPIO2
PA3_GPIO3 SSI1CLK
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7 MIIRXD1
PB0_GPIO8 SSI2TX CAN1TX U4TX
PB1_GPIO9 SSI2RX
PB2_GPIO10 SSI2CLK CAN1RX U4RX
PB3_GPIO11 SSI2FSS U1RX
PB4_GPIO12 CAN1TX SSI1TX
PB5_GPIO13 CAN1RX SSI1RX
PB6_GPIO14 MIICRS I2C0SDA U1TX SSI1CLK
PB7_GPIO15 I2C0SCL U1RX SSI1FSS
PD0_GPIO16 MIIRXD2 SSI0TX CAN1TX USB0EPEN
PD1_GPIO17 MIICOL SSI0RX CAN1RX USB0PFLT
PD2_GPIO18 SSI0CLK U1TX CAN0RX
PD3_GPIO19 SSI0FSS U1RX CAN0TX
PD4_GPIO20 U3TX CAN1TX
PD5_GPIO21 U3RX CAN1RX
PD6_GPIO22 I2C1SDA U1TX
PD7_GPIO23 I2C1SCL U1RX
PE0_GPIO24 SSI3TX CAN0RX SSI1TX
PE1_GPIO25 SSI3RX CAN0TX SSI1RX
PE2_GPIO26 SSI3CLK U2RX SSI1CLK
PE3_GPIO27 SSI3FSS U2TX SSI1FSS
PE4_GPIO28 U0RX EPI0S38(2) USB0EPEN
PE5_GPIO29 MIITXER U0TX USB0PFLT
PE6_GPIO30 MIIMDIO CAN0RX
PE7_GPIO31 MIIRXD3 CAN0TX
PF0_GPIO32 I2C0SDA TRACED2
PF1_GPIO33 I2C0SCL TRACED3
PF2_GPIO34 TRACECLK XCLKOUT
PF3_GPIO35 U0TX TRACED0
PF4_GPIO36 U0RX
PF5_GPIO37 MIITXEN
USB0VBUS PF6_GPIO38
PF7_GPIO39 CAN1TX
PG0_GPIO40 MIIRXD2 U4RX MIITXCK
PG1_GPIO41 MIIRXD1 U4TX MIITXER
USB0DM PG2_GPIO42
PG3_GPIO43 MIIRXDV TRACED1
PG4_GPIO44 CAN1RX
USB0DP PG5_GPIO45
USB0ID PG6_GPIO46
PG7_GPIO47 MIICRS
PH0_GPIO48 SSI3TX MIITXD3
PH1_GPIO49 MIIRXD0 SSI3RX MIITXD2
PH2_GPIO50 SSI3CLK MIITXD1
PH3_GPIO51 SSI3FSS MIITXD0
PH4_GPIO52 U3TX MIICOL
PH5_GPIO53 U3RX MIIPHYRST
PH6_GPIO54 MIITXEN SSI0TX MIIPHYINTR
PH7_GPIO55 MIITXCK SSI0RX MIIMDC
PJ0_GPIO56 SSI0CLK MIIMDIO
PJ1_GPIO57 MIIRXDV SSI0FSS MIIRXD3
PJ2_GPIO58 MIIRXCK SSI0CLK U0TX MIIRXD2
PJ3_GPIO59 MIIMDC SSI0FSS U0RX MIIRXD1
PJ4_GPIO60 MIICOL SSI1CLK MIIRXD0
PJ5_GPIO61 MIICRS SSI1FSS MIIRXDV
PJ6_GPIO62 MIIPHYINTR U2RX MIIRXER
PJ7_GPIO63/
XCLKIN
MIIPHYRST U2TX MIIRXCK
PC0_GPIO64 MIIRXD2
PC1_GPIO65 MIICOL
PC2_GPIO66 MIITXEN
PC3_GPIO67 MIITXCK
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PK0_GPIO72 SSI0TX
PK1_GPIO73 SSI0RX
PK2_GPIO74 SSI0CLK
PK3_GPIO75 SSI0FSS
PK4_GPIO76 MIITXEN SSI0TX
PK5_GPIO77 MIITXCK SSI0RX
PK6_GPIO78 MIITXER SSI0CLK
PK7_GPIO79 MIICRS SSI0FSS
PL0_GPIO80 MIIRXD3 SSI1TX
PL1_GPIO81 MIIRXD2 SSI1RX
PL2_GPIO82 MIIRXD1 SSI1CLK
PL3_GPIO83 MIIRXD0 SSI1FSS
PL4_GPIO84 MIICOL SSI3TX
PL5_GPIO85 MIIPHYRST SSI3RX
PL6_GPIO86 MIIPHYINTR SSI3CLK
PL7_GPIO87 MIIMDC SSI3FSS
PM0_GPIO88 MIIMDIO SSI2TX
PM1_GPIO89 MIITXD3 SSI2RX
PM2_GPIO90 MIITXD2 SSI2CLK
PM3_GPIO91 MIITXD1 SSI2FSS
PM4_GPIO92 MIITXD0
PM5_GPIO93 MIIRXDV
PM6_GPIO94 MIIRXER
PM7_GPIO95 MIIRXCK
PN0_GPIO96 I2C0SCL
PN1_GPIO97 I2C0SDA
PN2_GPIO98 U1RX
PN3_GPIO99 U1TX
PN4_GPIO100 U3TX
PN5_GPIO101 U3RX
PN6_GPIO102 U4RX EPI0S42(2) USB0EPEN
PN7_GPIO103 U4TX EPI0S43(2) USB0PFLT
PP0_GPIO104 I2C1SCL
PP1_GPIO105 I2C1SDA
PP2_GPIO106 I2C0SCL
PP3_GPIO107 I2C0SDA
PP4_GPIO108 I2C1SCL
PP5_GPIO109 I2C1SDA
PP6_GPIO110
PP7_GPIO111
PQ0_GPIO112
PQ1_GPIO113
PQ2_GPIO114 U0RX
PQ3_GPIO115 U0TX
PQ4_GPIO116 SSI1TX
PQ5_GPIO117 SSI1RX
PQ6_GPIO118
PQ7_GPIO119
PR0_GPIO120 SSI3TX
PR1_GPIO121 SSI3RX
PR2_GPIO122 SSI3CLK
PR3_GPIO123 SSI3FSS
PR4_GPIO124
PR5_GPIO125
PR6_GPIO126
PR7_GPIO127
PS0_GPIO128
PS1_GPIO129
PS2_GPIO130
PS3_GPIO131
PS4_GPIO132
PS5_GPIO133
PS6_GPIO134
PS7_GPIO135
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.

Table 6-29 GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1)

ANALOG MODE
(USB PINS)
DEVICE PIN NAME C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
PA0_GPIO0 GPIO0 EPWM1A
PA1_GPIO1 GPIO1 EPWM1B ECAP6
PA2_GPIO2 GPIO2 EPWM2A
PA3_GPIO3 GPIO3 EPWM2B ECAP5
PA4_GPIO4 GPIO4 EPWM3A
PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1
PA6_GPIO6 GPIO6 EPWM4A EPWMSYNCO
PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2
PB0_GPIO8 GPIO8 EPWM5A ADCSOCAO
PB1_GPIO9 GPIO9 EPWM5B ECAP3
PB2_GPIO10 GPIO10 EPWM6A ADCSOCBO
PB3_GPIO11 GPIO11 EPWM6B ECAP4
PB4_GPIO12 GPIO12 EPWM7A
PB5_GPIO13 GPIO13 EPWM7B
PB6_GPIO14 GPIO14 EPWM8A
PB7_GPIO15 GPIO15 EPWM8B
PD0_GPIO16 GPIO16 SPISIMOA
PD1_GPIO17 GPIO17 SPISOMIA
PD2_GPIO18 GPIO18 SPICLKA
PD3_GPIO19 GPIO19 SPISTEA
PD4_GPIO20 GPIO20 EQEP1A MDXA
PD5_GPIO21 GPIO21 EQEP1B MDRA
PD6_GPIO22 GPIO22 EQEP1S MCLKXA
PD7_GPIO23 GPIO23 EQEP1I MFSXA
PE0_GPIO24 GPIO24 ECAP1 EQEP2A
PE1_GPIO25 GPIO25 ECAP2 EQEP2B
PE2_GPIO26 GPIO26 ECAP3 EQEP2I
PE3_GPIO27 GPIO27 ECAP4 EQEP2S
PE4_GPIO28 GPIO28 SCIRXDA
PE5_GPIO29 GPIO29 SCITXDA
PE6_GPIO30 GPIO30 EPWM9A
PE7_GPIO31 GPIO31 EPWM9B
PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO
PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO
PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT
PF3_GPIO35 GPIO35 SCITXDA
PF4_GPIO36 GPIO36 SCIRXDA
PF5_GPIO37 GPIO37 ECAP2
USB0VBUS PF6_GPIO38 GPIO38
PF7_GPIO39 GPIO39
PG0_GPIO40 GPIO40
PG1_GPIO41 GPIO41
USB0DM PG2_GPIO42 GPIO42
PG3_GPIO43 GPIO43
PG4_GPIO44 GPIO44
USB0DP PG5_GPIO45 GPIO45
USB0ID PG6_GPIO46 GPIO46
PG7_GPIO47 GPIO47
PH0_GPIO48 GPIO48 ECAP5
PH1_GPIO49 GPIO49 ECAP6
PH2_GPIO50 GPIO50 EQEP1A
PH3_GPIO51 GPIO51 EQEP1B
PH4_GPIO52 GPIO52 EQEP1S
PH5_GPIO53 GPIO53 EQEP1I
PH6_GPIO54 GPIO54 SPISIMOA EQEP3A
PH7_GPIO55 GPIO55 SPISOMIA EQEP3B
PJ0_GPIO56 GPIO56 SPICLKA EQEP3S
PJ1_GPIO57 GPIO57 SPISTEA EQEP3I
PJ2_GPIO58 GPIO58 MCLKRA EPWM7A
PJ3_GPIO59 GPIO59 MFSRA EPWM7B
PJ4_GPIO60 GPIO60 EPWM8A
PJ5_GPIO61 GPIO61 EPWM8B
PJ6_GPIO62 GPIO62 EPWM9A
PJ7_GPIO63/
XCLKIN
GPIO63 EPWM9B
PC0_GPIO64 GPIO64 EQEP1A EQEP2I
PC1_GPIO65 GPIO65 EQEP1B EQEP2S
PC2_GPIO66 GPIO66 EQEP1S EQEP2A
PC3_GPIO67 GPIO67 EQEP1I EQEP2B
PC4_GPIO68 GPIO68
PC5_GPIO69 GPIO69
PC6_GPIO70 GPIO70
PC7_GPIO71 GPIO71
PK0_GPIO72 GPIO72 SPISIMOA
PK1_GPIO73 GPIO73 SPISOMIA
PK2_GPIO74 GPIO74 SPICLKA
PK3_GPIO75 GPIO75 SPISTEA
PK4_GPIO76 GPIO76
PK5_GPIO77 GPIO77
PK6_GPIO78 GPIO78
PK7_GPIO79 GPIO79
PL0_GPIO80 GPIO80
PL1_GPIO81 GPIO81
PL2_GPIO82 GPIO82
PL3_GPIO83 GPIO83
PL4_GPIO84 GPIO84
PL5_GPIO85 GPIO85
PL6_GPIO86 GPIO86
PL7_GPIO87 GPIO87
PM0_GPIO88 GPIO88
PM1_GPIO89 GPIO89
PM2_GPIO90 GPIO90
PM3_GPIO91 GPIO91
PM4_GPIO92 GPIO92 MDXA
PM5_GPIO93 GPIO93 MDRA
PM6_GPIO94 GPIO94 MCLKXA
PM7_GPIO95 GPIO95 MFSXA
PN0_GPIO96 GPIO96 MCLKRA
PN1_GPIO97 GPIO97 MFSRA
PN2_GPIO98 GPIO98
PN3_GPIO99 GPIO99
PN4_GPIO100 GPIO100
PN5_GPIO101 GPIO101
PN6_GPIO102 GPIO102
PN7_GPIO103 GPIO103
PP0_GPIO104 GPIO104 I2CSDAA
PP1_GPIO105 GPIO105 I2CSCLA
PP2_GPIO106 GPIO106 EQEP1A
PP3_GPIO107 GPIO107 EQEP1B
PP4_GPIO108 GPIO108 EQEP1S
PP5_GPIO109 GPIO109 EQEP1I
PP6_GPIO110 GPIO110 EQEP2A EQEP3S
PP7_GPIO111 GPIO111 EQEP2B EQEP3I
PQ0_GPIO112 GPIO112 EQEP2I EQEP3A
PQ1_GPIO113 GPIO113 EQEP2S EQEP3B
PQ2_GPIO114 GPIO114
PQ3_GPIO115 GPIO115
PQ4_GPIO116 GPIO116
PQ5_GPIO117 GPIO117
PQ6_GPIO118 GPIO118 SCITXDA
PQ7_GPIO119 GPIO119 SCIRXDA
PR0_GPIO120 GPIO120
PR1_GPIO121 GPIO121
PR2_GPIO122 GPIO122
PR3_GPIO123 GPIO123
PR4_GPIO124 GPIO124 EPWM7A
PR5_GPIO125 GPIO125 EPWM7B
PR6_GPIO126 GPIO126 EPWM8A
PR7_GPIO127 GPIO127 EPWM8B
PS0_GPIO128 GPIO128 EPWM9A
PS1_GPIO129 GPIO129 EPWM9B
PS2_GPIO130 GPIO130 EPWM10A
PS3_GPIO131 GPIO131 EPWM10B
PS4_GPIO132 GPIO132 EPWM11A
PS5_GPIO133 GPIO133 EPWM11B
PS6_GPIO134 GPIO134 EPWM12A
PS7_GPIO135 GPIO135 EPWM12B
Blank fields represent Reserved functions.

GPIO_MUX2

The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed through a separate set of registers from those used to program GPIO_MUX1.

The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G. They are accessible by the C28x CPU only. The middle portion of Figure 6-17 shows set G of Control Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register selects one of six possible digital output signals from analog comparators, or one of eight general-purpose GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 6-30 for the mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2.

Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to “00”, “01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00” (Peripheral Mode 0) assigns pin GPIO194 to internal signal GPIO194 (digital GPIO). Setting bits 5–4 of the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO194 to internal signal COMP6OUT coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently available.

Table 6-30 GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)(1)

DEVICE PIN NAME C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
GPIO192 GPIO192
GPIO193 GPIO193 COMP1OUT
GPIO194 GPIO194 COMP6OUT
GPIO195 GPIO195 COMP2OUT
GPIO196 GPIO196 COMP3OUT
GPIO197 GPIO197 COMP4OUT
GPIO198 GPIO198
GPIO199 GPIO199 COMP5OUT
Blank fields represent Reserved functions.
F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 ADC_GPIO_COMP_prs820.gif Figure 6-17 Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2

AIO_MUX1

The 12 pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. While AIO_MUX1 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1 block is programmed through a separate set of registers from those used to program AIO_MUX2.

The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU only. The top portion of Figure 6-17 shows Control Subsystem registers and muxing logic for the associated 12 AIO pins. The AIOMUX1 register selects 1 of 12 possible analog input signals or 1 of 6 general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting the direction for each of the bits (read or write). See Table 6-31 for the mapping of analog inputs and AIOs to the 12 pins of AIO_MUX1.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1 register to ‘0’ assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1 register to ‘1’ assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are “don’t cares”.

Table 6-31 AIO_MUX1 Pin Assignments (C28x AIO Modes)(1)(2)

DEVICE PIN NAME C28x AIO MODE 0(3) C28x AIO MODE 1(4)
ADC1INA0 ADC1INA0
ADC1INA2 AIO2 ADC1INA2, COMPA1
ADC1INA3 ADC1INA3
ADC1INA4 AIO4 ADC1INA4, COMPA2
ADC1INA6 AIO6 ADC1INA6, COMPA3
ADC1INA7 ADC1INA7
ADC1INB0 ADC1INB0
ADC1INB2 AIO10 ADC1INB2, COMPB1
ADC1INB3 ADC1INB3
ADC1INB4 AIO12 ADC1INB4, COMPB2
ADC1INB6 AIO14 ADC1INB6, COMPB3
ADC1INB7 ADC1INB7
Blank fields represent Reserved functions.
For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
AIO Mode 0 represents digital general-purpose inputs or outputs.
AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.

AIO_MUX2

The 12 pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. While AIO_MUX2 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2 block is programmed through a separate set of registers from those used to program AIO_MUX1.

The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU only. The bottom portion of Figure 6-17 shows Control Subsystem registers and muxing logic for the associated 12 AIO pins. The AIOMUX2 register selects 1 of 12 possible analog input signals or 1 of 6 general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting the direction for each of the bits (read or write). See Table 6-32 for the mapping of analog inputs and AIOs to the 12 pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2 register to ‘0’ assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2 register to ‘1’ assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are “don’t cares”.

Table 6-32 AIO_MUX2 Pin Assignments (C28x AIO Modes)(1)(2)

DEVICE PIN NAME C28x AIO MODE 0(3) C28x AIO MODE 1(4)
ADC2INA0 ADC2INA0
ADC2INA2 AIO18 ADC2INA2, COMPA4
ADC2INA3 ADC2INA3
ADC2INA4 AIO20 ADC2INA4, COMPA5
ADC2INA6 AIO22 ADC2INA6, COMPA6
ADC2INA7 ADC2INA7
ADC2INB0 ADC2INB0
ADC2INB2 AIO26 ADC2INB2, COMPB4
ADC2INB3 ADC2INB3
ADC2INB4 AIO28 ADC2INB4, COMPB5
ADC2INB6 AIO30 ADC2INB6, COMPB6
ADC2INB7 ADC2INB7
Blank fields represent Reserved functions.
For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
AIO Mode 0 represents digital general-purpose inputs or outputs.
AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.

Emulation/JTAG

Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port and the 5-pin Cortex-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used to connect to debug tools through the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin Cortex-M3 ITM port can only be accessed through the TI 20-pin JTAG header.

The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1 signals should be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). The JTAG port is TI’s standard debug port.

The ITM port uses five GPIO pins that can be mapped to internal Cortex-M3 ITM trace signals: TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug.

TI emulators, and those from other manufacturers, can connect to Concerto devices through TI’s 14-pin JTAG header or 20-pin JTAG header. See Figure 6-18 to see how the 14-pin JTAG header connects to the JTAG port signals in Concerto. The 14-pin header does not support the ITM debug mode.

Figure 6-19 shows two possible ways to connect the 20-pin header to the emulation pins in Concerto. The left side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the 14-pin header was connected. The JTAG EMU0 and EMU1 signals are mapped to the corresponding terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left unconnected and the ITM trace mode is not available.

The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of seven JTAG signals. The EMU0 and EMU1 signals in Concerto are left unconnected in this mode; thus, the emulation functions associated with these two signals are not available when debugging with ITM trace.

F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 jtag14_prs825.gif
The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 6-18 Connecting to TI 14-Pin JTAG Emulator Header
F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2 jtag20_prs825.gif
The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 6-19 Connecting to TI 20-Pin JTAG Emulator Header

Code Security Module

The Code Security Module (CSM) is a security feature incorporated in Concerto devices. The CSM prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory is not protected—that is, the contents of the memory could be read by any means [for example, by using a debugging tool such as Code Composer Studio™ Integrated Development Environment (IDE)].

Functional Description

The security module restricts the CPU access to on-chip secure memory without interrupting or stalling CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This process, in effect, blocks read and write access to various memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-chip secure memories and prevents unauthorized copying of proprietary code or data.

The zone is secure when CPU access to the on-chip secure memories associated with that zone is restricted. When secure, two levels of protection are possible, depending on where the program counter is currently pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (that is, through the emulator). This process allows secure code to access secure data. Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User code can dynamically jump in and out of secure memory, thereby allowing secure function calls from unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main program loop is run from unsecure memory.

The code security mechanism present in this device offers dual-zone security for the Cortex-M3 code and single-zone security for the C28x code. In case of dual-zone security on the master subsystem, the different secure memories (RAMs and flash sectors) can be assigned to different security zones by configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the GRABSECT registers.

Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by executing the password match flow (PMF).

The CSM password for each zone is stored in its dedicated flash sector. The password storage locations in the flash sector store the CSM password. The password is selected by the system designer. If the password locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Because new flash devices have erased flash (all ones), only a read of the password locations is required to bring any zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase routine can result in either an all-zero or unknown password. If a device is reset when the password locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of all zeros will seriously limit the user’s ability to debug secure code or reprogram the flash.

NOTE

If a device is reset while the password locations of a zone contain all zeros or an unknown value, that zone will be permanently locked unless a method to run the flash erase routine from secure SARAM is embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid introducing a security hole.

µCRC Module

The µCRC module is part of the master subsystem. This module can be used by Cortex-M3 software to compute CRC on data and program, which are stored at memory locations that are addressable by Cortex-M3. On this device, the Cortex-M3 Flash Bank and ROM are mapped to the code space that is only accessed by the ICODE/DCODE bus of Cortex-M3; and RAMs are mapped on the SRAM space that is accessible by the SYSTEM bus. Hence, the µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program.

Functional Description

The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. To allow interrupts execution in between CRC calculations for a block of data and to discard the Cortex-M3 literal pool accesses in between executions of the program (which reads data for CRC calculation), the Cortex-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The µCRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to mirrored memory space. After grabbing, the µCRC module performs the CRC calculation on the grabbed data and updates the µCRC Result Register (µCRCRES). This register can be read at any time to get the calculated CRC for all the previous read data. The µCRC module only supports CRC calculation for byte accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to all the data. For half-word and word accesses, the µCRC module discards the data and does not update the µCRCRES register.

NOTE

If a read to a mirrored address space is thrown from the debugger (Code Composer Studio or any other debug platform), the µCRC module ignores the read data and does not update the CRC result for that particular read.

CRC Polynomials

The following are the CRC polynomials that are supported by the µCRC module:

  • CRC8 Polynomial = 0x07
  • CRC16 Polynomial-1 = 0x8005
  • CRC16 Polynomial-2 = 0x1021
  • CRC32 Polynomial = 0x04C11DB7

CRC Calculation Procedure

The software procedure for calculating CRC for a set of data that is stored in Cortex-M3 addressable memory space is as follows:

  1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of CRC in nested interrupt
  2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register (µCRCCONTROL) to "1"
  3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC Configuration Register (µCRCCONFIG)
  4. Read the data from memory locations for which CRC needs to be calculated using mirrored address
  5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC from the stack and store this value into the µCRC Result Register (uCRCRES)

CRC Calculation for Data Stored In Secure Memory

This device has dual-zone security for the Cortex-M3 subsystem. Because ZoneX (X → 1/2) software does not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is running from same secure zone, the software cannot read the data stored in Exe-Only sectors. However, hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the read access for this data is initiated by code running from same secure zone. These reads are just dummy reads and, in this case, read data only goes to the µCRC module, not to the CPU.