SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C Host-Side Control Interface

If I2C is used as the host-side communication protocol, the maximum number of FPC202 devices which can share a single I2C bus is 14. This allows for controlling up to 28 downstream ports through a single I2C bus.

I2C is an addressed interface. To reduce pin count and simplify integration, the FPC202 has an auto-addressing scheme whereby all FPC202s in a system will take on a unique address without requiring dedicated address pins. This is accomplished by connecting one FPC202’s CTRL4 (ADDR_DONE_N) pin to the subsequent FPC202’s CTRL3 (SET_ADDR_N) pin. The first FPC202 will connect CTRL3 (SET_ADDR_N) to GND, and the final FPC202 will connect CTRL4 (ADDR_DONE_N) to GND, as shown in Figure 7-4.

GUID-B19B1818-AC1D-4D1C-B517-9CC4A57992C5-low.gifFigure 7-4 FPC202 Connection Diagram For Unique Addressing in I2C Mode

For I2C host-side control interface implementations, the host controller must first configure each FPC202 device to have a unique address. The CTRL3 (SET_ADDR_N) pin is internally pulled to high logic (regardless of the EN pin status) and the FPC202 device will not respond to any I2C transactions until this pin is pulled low. Once it is driven to low logic, the device will respond to the default I2C 8-bit address (0x1E). A single I2C write to the FPC202 will reassign a new I2C address, and once this is done, the FPC202 will drive low logic with the CTRL4 pin (ADDR_DONE_N) which allows the next FPC202 in the daisy chain to be programmed using the default address. Until this address re-assignment happens, the CTRL4 (ADDR_DONE_N) pin is high-Z.

This scheme allows each FPC202 to take a unique I2C address without any contention on the bus. The addresses may be programmed in any order except for the default 8-bit address (0x1E) which must be assigned to the last device in the daisy chain, or else two FPC202s will respond to 0x1E and there will be bus contention. The state of the CTRL3 (SET_ADDR_N) pin does not matter after the address is reprogrammed (this pin is then used to transfer the LED clock for blinking synchronization). Once the new address is programmed, it becomes fixed and may no longer be changed by a new register write. Only power cycling the device or toggling the EN pin will restore the device to the default re-programmable address.

The I2C address space for FPC202 applications is designed such that each FPC202, each port being controlled, and each logical device address within each port is accessible to the host controller through a unique I2C address. For a system where one or more FPC202s are used to control multiple ports (up to two ports per FPC202), the address of each FPC202 and the address of each each downstream port is shown in Table 7-6.

All FPC202 devices respond to 8-bit I2C address 0x02. This allows the host controller to broadcast write to all FPC202 devices simultaneously.

Table 7-6 I2C 8-Bit Address Map
FPC202 INSTANCE NUMBER FPC202 SELF-ADDRESS PORT 0 PORT 1
PRIMARY DEVICE
Default = 0xA0(1)
SECONDARY DEVICE
Default = 0xA2(1)
PRIMARY DEVICE
Default = 0xA0(1)
SECONDARY DEVICE
Default = 0xA2(1)
ALL 0x02
0 0x04 0x20 0x22 0x28 0x2A
1 0x06 0x30 0x32 0x38 0x3A
2 0x08 0x40 0x42 0x48 0x4A
3 0x0A 0x50 0x52 0x58 0x5A
4 0x0C 0x60 0x62 0x68 0x6A
5 0x0E 0x70 0x72 0x78 0x7A
6 0x10 0x80 0x82 0x88 0x8A
7 0x12 0x90 0x92 0x98 0x9A
8 0x14 0xA0 0xA2 0xA8 0xAA
9 0x16 0xB0 0xB2 0xB8 0xBA
10 0x18 0xC0 0xC2 0xC8 0xCA
11 0x1A 0xD0 0xD2 0xD8 0xDA
12 0x1C 0xE0 0xE2 0xE8 0xEA
13 0x1E 0xF0 0xF2 0xF8 0xFA
Device addresses are programmable. By default, the device 0 address is 0xA0 and the device 1 address is 0xA2. Request access to the FPC202 Programmer's Guide (SNLU229) here for more details.

The timing specification for an I2C transaction is described in Figure 7-5.

GUID-52889F1F-565C-4DED-A791-7BEC802424E0-low.gifFigure 7-5 I2C Timing Diagram