SLASE82A June   2015  – July 2015 HD3SS3411-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
      1. 8.4.1 AC Coupling Capacitors
    5. 8.5 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Routes
      2. 10.1.2 General Routing/Placement Rules
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The HD3SS3411-Q1 is a high-speed bi-directional passive switch in mux or demux configurations. Based on control pin SEL, the device switches one differential channels between Port B or Port C to Port A.

The HD3SS3411-Q1 is a generic analog differential passive switch that can work for any high speed interface applications as long as it is biased at a common mode voltage range of 0 V to 2 V and has differential signaling with differential amplitude up to 1800 mVpp. The device employs an adaptive tracking that ensures the channel remains unchanged for entire common mode voltage range.

Table 1. MUX Pin Connections(1)

Ap Bp Cp
An Bn Cn
The HD3SS3411-Q1 can tolerate polarity inversions for all differential signals on Ports A, B and C. Care should be taken to ensure the same polarity is maintained on Port A vs. Port B/C.

Functional Block Diagram

HD3SS3411-Q1 fbd_slase82.gif

Feature Description

Output Enable and Power Savings

The HD3SS3411-Q1 has two power modes, normal operating mode and shutdown mode. During shutdown mode, the device consumes very-little current to save the maximum power. The OEn control pin is used to toggle between the two modes.

HD3SS3411-Q1 consumes < 2 mW of power when operational and has a shutdown mode exercisable by the OEn pin resulting < 20 µW.

Device Functional Modes

The OEn control pin selects the functional mode of HD3SS3411-Q1. To enter standby/shutdown mode, the OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control pin should be pulled low to GND or dynamically controlled to switch between H or L.

Table 2. Device Power Modes

OEn Device State Signal Pins
L Normal Normal
H Shutdown Tri-stated