SLLSEC4B June   2013  – August 2016 HVDA551-Q1 , HVDA553-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 Using the HVDA553 With Split Termination
      3. 8.3.3 Protection Features
        1. TXD Dominant State Time Out
        2. Thermal Shutdown
        3. Undervoltage Lockout or Unpowered Device
        4. Floating Pins
        5. CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode With RXD Wake-Up Request
        1. RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
      4. 8.4.4 Driver and Receiver Function Tables
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level in Low-Power Mode
        1. Design Requirements
        2. Detailed Design Procedure
          1. Loop Propagation Delay
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

HVDA551 and HVDA553 families come with high on-chip IEC ESD protection, but if higher levels are desired, external TVS diodes can be used. TVS diodes and bus-filtering capacitors must be placed as close as possible to board connectors to prevent noisy transient events into PCB. Placement at the connector also prevents these harsh transient events from propagating further into the PCB and system. Use VCC and ground planes to provide low inductances. High frequency current follows the path of least impedance and not the path of least resistance. TI recommends designing the bus protection components in the direction of the signal path. Do not force transient current to divert from signal path to reach protection device.

  • Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise from propagating onto the board. In this layout example, a transient voltage suppression (TVS) device, D1, has been used for added protection. The production solution can be either bidirectional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the CANH and CANL lines between the transceiver U1 and connector J1.
  • Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
  • Use supply (VCC) and ground planes to provide low inductance.
  • NOTE

    High-frequency currents follows the path of least impedance and not the path of least resistance.

  • Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
  • Bypass and bulk capacitors must be placed as close as possible to the supply terminals of transceiver, examples are C1 and C2 on the VCC supply and C6 and C7 on the VIO supply.
  • Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground through capacitor C3. Split termination provides common-mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, take additional care to ensure the terminating node is not removed from the bus thus also removing the termination.
  • To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not required.
  • Terminal 1: R1 is shown optionally for the TXD input of the device. If an open-drain host processor is used, this is mandatory to ensure the bit timing into the device is met.
  • Terminal 5: For devices with a VIO input, bypass capacitors must be placed as close to the pin as possible (example C6 and C7). In devices without a VIO input, this pin is not internally connected and can be left floating or tied to any existing net (for example, a split pin connection).
  • Terminal 8 is shown assuming the mode terminal, STB, will be used. If the device is only used in normal mode, R4 is not needed and R5 could be used for the pulldown resistor to GND.

11.2 Layout Example

HVDA551-Q1 HVDA553-Q1 Layout.gif Figure 27. HVDA551 Layout Example Recommendation