SBOS247C June   2002  – November 2015 INA217

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±15 V
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic Connections
      2. 7.3.2 Gain-Set Resistor
      3. 7.3.3 Noise Performance
      4. 7.3.4 Input Considerations
      5. 7.3.5 Offset Voltage Trim
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DW Package
16-Pin SOIC
Top View
INA217 po_01_sbos247.gif
P Package
8-Pin PDIP
Top View
INA217 po_02_sbos247.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
PDIP
NC 1 — No internal connection
RG1 2 I Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15
NC 3 — No internal connection
VIN– 4 I Inverting input
VIN+ 5 I Non-inverting input
NC 6 — No internal connection
V– 7 I negative power supply
NC 8 — No internal connection
NC 9 — No internal connection
REF 10 I Reference input
VOUT 11 O Output
NC 12 — No internal connection
V+ 13 I Positive power supply
NC 14 — No internal connection
RG2 15 I Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15
NC 16 — No internal connection
SOIC
RG1 1 I Gain setting pin, for gains greater than one, connect an external resistor between pins 1 and 8
VIN– 2 I Inverting input
VIN+ 3 I Non-inverting input
V– 4 I negative power supply
REF 5 I Reference input
VOUT 6 O Output
V+ 7 I Positive power supply
RG2 8 I Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15