SBOS612A February   2014  – March 2014 INA225

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Selecting A Shunt Resistor
        1. 7.3.1.1 Selecting A Current-Sense Resistor Example
        2. 7.3.1.2 Optimizing Power Dissipation versus Measurement Accuracy
      2. 7.3.2 Programmable Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Filtering
      2. 7.4.2 Shutting Down the Device
      3. 7.4.3 Using the Device with Common-Mode Transients Above 36 V
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Microcontroller-Configured Gain Selection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Unidirectional Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Bidirectional Operation
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range, unless otherwise noted.
MIN MAX UNIT
Supply voltage +40 V
Analog inputs, VIN+, VIN–(2) Differential (VIN+) – (VIN–) –40 +40 V
Common-mode(3) GND – 0.3 +40 V
REF, GS0, and GS1 inputs GND – 0.3 (VS) + 0.3 V
Output GND – 0.3 (VS) + 0.3 V
Temperature Operating, TA –55 +150 °C
Junction, TJ +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– terminals, respectively.
(3) Input voltage at any terminal may exceed the voltage shown if the current at that terminal is limited to 5 mA.

6.2 Handling Ratings

MIN MAX UNIT
TSTG Storage temperature range –65 +150 °C
VESD(1) Human body model (HBM) stress voltage(2) 4 kV
Charged device model (CDM) stress voltage(3) 1 kV
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 4-kV HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 1-kV CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.
MIN NOM MAX UNIT
VCM Common-mode input voltage 12 V
VS Operating supply voltage 5 V
TA Operating free-air temperature –40 +125 °C

6.4 Thermal Information

THERMAL METRIC INA225 UNIT
DGK (MSOP)
8 TERMINALS
θJA Junction-to-ambient thermal resistance 163.6 °C/W
θJCtop Junction-to-case (top) thermal resistance 57.7
θJB Junction-to-board thermal resistance 84.7
ψJT Junction-to-top characterization parameter 6.5
ψJB Junction-to-board characterization parameter 83.2
θJCbot Junction-to-case (bottom) thermal resistance N/A

6.5 Electrical Characteristics

At TA = +25°C, VSENSE = VIN+ – VIN–, VS = +5 V, VIN+ = 12 V, and VREF = VS / 2, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
INPUT
VCM Common-mode input range TA = –40°C to +125°C 0 36 V
CMR Common-mode rejection VIN+ = 0 V to +36 V, VSENSE = 0 mV,
TA = –40°C to +125°C		 95 105 dB
VOS Offset voltage, RTI(1) VSENSE = 0 mV ±75 ±150 μV
dVOS/dT RTI vs temperature TA = –40°C to +125°C 0.2 0.5 μV/°C
PSRR Power-supply rejection ratio VSENSE = 0 mV, VREF = 2.5 V,
VS = 2.7 V to 36 V		 ±0.1 ±1 μV/V
IB Input bias current VSENSE = 0 mV 55 72 85 μA
IOS Input offset current VSENSE = 0 mV ±0.5 μA
VREF Reference input range TA = –40°C to +125°C 0 VS V
OUTPUT
G Gain 25, 50, 100, 200 V/V
EG Gain error Gain = 25 V/V and 50 V/V, VOUT = 0.5 V to
VS – 0.5 V, TA = –40°C to +125°C		 ±0.05% ±0.15%
Gain = 100 V/V, VOUT = 0.5 V to VS – 0.5 V,
TA = –40°C to +125°C		 ±0.1% ±0.2%
Gain = 200 V/V, VOUT = 0.5 V to VS – 0.5 V,
TA = –40°C to +125°C		 ±0.1% ±0.3%
Gain error vs temperature G = 25 V/V, 50 V/V, 100 V/V,
TA = –40°C to +125°C		 3 10 ppm/°C
G = 200 V/V, TA = –40°C to +125°C 5 15
Nonlinearity error VOUT = 0.5 V to VS – 0.5 V ±0.01%
Maximum capacitive load No sustained oscillation 1 nF
VOLTAGE OUTPUT(2)
Swing to VS power-supply rail RL = 10 kΩ to GND, TA = –40°C to +125°C VS – 0.05 VS – 0.2 V
Swing to GND(3) VREF = VS / 2, all gains, RL = 10 kΩ to GND,
TA = –40°C to +125°C		 VGND + 5 VGND + 10 mV
VREF = GND, gain = 25 V/V, RL = 10 kΩ to GND,
TA = –40°C to +125°C		 VGND + 7 mV
VREF = GND, gain = 50 V/V, RL = 10 kΩ to GND,
TA = –40°C to +125°C		 VGND + 15 mV
VREF = GND, gain = 100 V/V, RL = 10 kΩ to GND,
TA = –40°C to +125°C		 VGND + 30 mV
VREF = GND, gain = 200 V/V, RL = 10 kΩ to GND,
TA = –40°C to +125°C		 VGND + 60 mV
FREQUENCY RESPONSE
BW Bandwidth Gain = 25 V/V, CLOAD = 10 pF 250 kHz
Gain = 50 V/V, CLOAD = 10 pF 200 kHz
Gain = 100 V/V, CLOAD = 10 pF 125 kHz
Gain = 200 V/V, CLOAD = 10 pF 70 kHz
SR Slew rate 0.4 V/μs
NOISE, RTI(1)
Voltage noise density 50 nV/√Hz
DIGITAL INPUT
Ci Input capacitance 3 pF
Leakage input current 0 ≤ VIN ≤ VS 1 2 μA
VIL Low-level input logic level 0 0.6 V
VIH High-level input logic level 2 VS V
POWER SUPPLY
VS Operating voltage range TA = –40°C to +125°C +2.7 +36 V
IQ Quiescent current VSENSE = 0 mV 300 350 μA
IQ over temperature TA = –40°C to +125°C 375 μA
TEMPERATURE RANGE
Specified range –40 +125 °C
Operating range –55 +150 °C
(1) RTI = referred-to-input.
(2) See Typical Characteristic curve, Output Voltage Swing vs Output Current (Figure 10).
(3) See Typical Characteristic curve, Unidirectional Output Voltage Swing vs. Temperature (Figure 14)

6.6 Typical Characteristics

At TA = +25°C, VS = +5 V, VIN+ = 12 V, and VREF = VS / 2, unless otherwise noted.
C001_SBOS612.png
Figure 1. Input Offset Voltage Production Distribution
C003_SBOS612.png
Figure 3. Common-Mode Rejection Production Distribution
C005_SBOS612.png
Figure 5. Gain Error Production Distribution (Gain = 25 V/V)
C007_SBOS612.png
Figure 7. Gain Error Production Distribution
(Gain = 100 V/V)
C009_SBOS612.png
Figure 9. Gain Error vs Temperature
C011_SBOS612.png
VCM = 0 V VREF = 2.5 V VSENSE = 0 mV, Shorted
VS = 5 V + 250-mV Sine Disturbance
Figure 11. Power-Supply Rejection Ratio vs Frequency
C013_SBOS612.png
Figure 13. Output Voltage Swing vs Output Current
C014_SBOS612.png
Figure 15. Input Bias Current vs Common-Mode Voltage
(Supply Voltage = +5 V)
C016_SBOS612.png
VS = 5 V VCM = 12 V
Figure 17. Input Bias Current vs Temperature
C018_SBOS612.png
Figure 19. Quiescent Current vs Supply Voltage
C020_SBOS612.png
VS = ± 2.5 V VCM = 0 V VSENSE = 0 mV, Shorted
Figure 21. 0.1-Hz to 10-Hz Voltage Noise
(Referred-to-Input)
C022_SBOS612.png
Figure 23. Step Response
(Gain = 50 V/V, 2-VPP Output Step)
C024_SBOS612.png
Figure 25. Step Response
(Gain = 200 V/V, 2-VPP Output Step)
C026_SBOS612.png
VDIFF = 20 mV VOUT at 25-V/V Gain = 500 mV
VOUT at 100-V/V Gain = 2 V
Figure 27. Gain Change Output Response
(Gain = 25 V/V to 100 V/V)
C028_SBOS612.png
VDIFF = 20 mV VOUT at 100-V/V Gain = 2 V
VOUT at 200-V/V Gain = 4 V
Figure 29. Gain Change Output Response
(Gain = 100 V/V to 200 V/V)
C030_SBOS612.png
Figure 31. Gain Change Output Response From Saturation
(Gain = 100 V/V to 25 V/V)
C032_SBOS612.png
Figure 33. Gain Change Output Response From Saturation
(Gain = 200 V/V to 100 V/V)
C034_SBOS612.png
Figure 35. Start-Up Response
C002_SBOS612.png
Figure 2. Input Offset Voltage vs Temperature
C004_SBOS612.png
Figure 4. Common-Mode Rejection Ratio vs Temperature
C006_SBOS612.png
Figure 6. Gain Error Production Distribution (Gain = 50 V/V)
C008_SBOS612.png
Figure 8. Gain Error Production Distribution
(Gain = 200 V/V)
C010_SBOS612.png
VCM = 0 V VSENSE = 15 mVPP
Figure 10. Gain vs Frequency
C012_SBOS612.png
VS = 5 V VREF = 2.5 V VSENSE = 0 mV, Shorted
VCM = 1-V Sine Wave
Figure 12. Common-Mode Rejection Ratio vs Frequency
C038_SBOS612.png
Unidirectional, REF = GND Bidirectional, REF > GND
Figure 14. Unidirectional Output Voltage Swing vs. Temperature
C015_SBOS612.png
Figure 16. Input Bias Current vs Common-Mode Voltage
(Supply Voltage = 0 V, Shutdown)
C017_SBOS612.png
Figure 18. Quiescent Current vs Temperature
C019_SBOS612.png
VS = ± 2.5 V VREF = 0 V VSENSE = 0 mV, Shorted
Figure 20. Input-Referred Voltage Noise vs Frequency
C021_SBOS612.png
Figure 22. Step Response
(Gain = 25 V/V, 2-VPP Output Step)
C023_SBOS612.png
Figure 24. Step Response
(Gain = 100 V/V, 2-VPP Output Step)
C025_SBOS612.png
VDIFF = 20 mV VOUT at 25-V/V Gain = 500 mV
VOUT at 50-V/V Gain = 1 V
Figure 26. Gain Change Output Response
(Gain = 25 V/V to 50 V/V)
C027_SBOS612.png
VDIFF = 20 mV VOUT at 50-V/V Gain = 1 V
VOUT at 200-V/V Gain = 4 V
Figure 28. Gain Change Output Response
(Gain = 50 V/V to 200 V/V)
C029_SBOS612.png
Figure 30. Gain Change Output Response From Saturation
(Gain = 50 V/V to 25 V/V)
C031_SBOS612.png
Figure 32. Gain Change Output Response From Saturation
(Gain = 200 V/V to 50 V/V)
C033_SBOS612.png
Figure 34. Common-Mode Voltage Transient Response