SBOSA29A June   2020  – November 2023 INA281

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Amplifier Input Common-Mode Signal
        1. 6.3.1.1 Input-Signal Bandwidth
        2. 6.3.1.2 Low Input Bias Current
        3. 6.3.1.3 Low VSENSE Operation
        4. 6.3.1.4 Wide Fixed Gain Output
        5. 6.3.1.5 Wide Supply Range
    4. 6.4 Device Functional Modes
      1. 6.4.1 Unidirectional Operation
      2. 6.4.2 High Signal Throughput
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 RSENSE and Device Gain Selection
      2. 7.1.2 Input Filtering
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Overload Recovery With Negative VSENSE
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.2 Input Filtering

Note:

Input filters are not required for accurate measurements using the INA281-Q1INA281, and use of filters in this location is not recommended. If filter components are used on the input of the amplifier, follow the guidelines in this section to minimize the effects on performance.

Based strictly on user design requirements, external filtering of the current signal may be desired. The initial location that can be considered for the filter is at the output of the current-sense amplifier. Although placing the filter at the output satisfies the filtering requirements, this location changes the low output impedance measured by any circuitry connected to the output voltage pin. The other location for filter placement is at the current-sense amplifier input pins. This location also satisfies the filtering requirement, but the components must be carefully selected to minimally impact device performance. Figure 7-1 shows a filter placed at the input pins.

GUID-E7DA1419-046B-476A-8655-3F5C7B73909C-low.gifFigure 7-1 Filter at Input Pins

External series resistance provides a source of additional measurement error, so keep the value of these series resistors to 10 Ω or less to reduce loss of accuracy. The internal bias network shown in Figure 7-1 creates a mismatch in input bias currents (see Figure 5-7, Figure 5-8, and Figure 5-9) when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, a mismatch is created in the voltage drop across the filter resistors. This voltage is a differential error voltage in the shunt resistor voltage. In addition to the absolute resistor value, mismatch resulting from resistor tolerance can significantly impact the error because this value is calculated based on the actual measured resistance.

The measurement error expected from the additional external filter resistors can be calculated using Equation 4, and the gain error factor is calculated using Equation 5.

Equation 4. GUID-0A092707-4731-4945-B32C-94C91EBFA501-low.gif

The gain error factor, shown in Equation 4, can be calculated to determine the gain error introduced by the additional external series resistance. Equation 4 calculates the deviation of the shunt voltage, resulting from the attenuation and imbalance created by the added external filter resistance. Table 7-2 provides the gain error factor and gain error for several resistor values.

Equation 5. GUID-0A93BCEA-D402-492A-B130-4581DD6C85C8-low.gif

Where:

  • RIN is the external filter resistance value.
  • R1 is the INA281-Q1 input resistance value specified in Table 6-1.
  • RB in the internal bias resistance, which is 6600 Ω ± 20%.
Table 7-2 Example Gain Error Factor and Gain Error for 10-Ω External Filter Input Resistors
DEVICE (GAIN)GAIN ERROR FACTORGAIN ERROR (%)
A1 devices (20)0.99658–0.34185
A2 devices (50)0.99598–0.40141
A3 devices (100)0.99598–0.40141
A4 devices (200)0.99499–0.50051
A5 devices (500)0.99203–0.79663