SBOS464B september   2019  – june 2023 INA333-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Offset Correction
      2. 7.3.2 Input Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode Range
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Gain
        2. 8.2.2.2 Offset Trimming
        3. 8.2.2.3 Noise Performance
        4. 8.2.2.4 Input Bias Current Return Path
        5. 8.2.2.5 Low Voltage Operation
        6. 8.2.2.6 Single-Supply Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 TINA-TI Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Setting the Gain

The gain of the INA333-Q1 is set by a single external resistor, RG, connected between pins 1 and 8. The value of RG is selected according to Equation 1:

Equation 1. G = 1 + (100 kΩ / RG)

Table 8-1 lists several commonly-used gains and resistor values. The 100 kΩ in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA333-Q1.

The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of RG to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance and contribute additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. To maintain stability, avoid parasitic capacitance greater than a few picofarads at the RG connections. Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency.

Table 8-1 Commonly Used Gains and Resistor Values
DESIRED GAINRG (Ω)NEAREST 1% RG (Ω)
1NC(1)NC
2100k100k
525k24.9k
1011.1k11k
205.26k5.23k
502.04k2.05
1001.01k1k
200502.5499
500200.4200
1000100.1100
(1) NC denotes no connection. When using the SPICE model, the simulation does not converge unless a resistor is connected to the RG pins; use a very large resistor value.