SLLSFJ0F January   2020  – February 2023 ISO6720 , ISO6721 , ISO6721R

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V Supply
    10. 6.10 Supply Current Characteristics—5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply 
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Electrical Characteristics—1.8-V Supply
    16. 6.16 Supply Current Characteristics—1.8-V Supply
    17. 6.17 Switching Characteristics—5-V Supply
    18. 6.18 Switching Characteristics—3.3-V Supply
    19. 6.19 Switching Characteristics—2.5-V Supply
    20. 6.20 Switching Characteristics—1.8-V Supply
    21. 6.21 Insulation Characteristics Curves
    22. 6.22 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
8-D
IEC 60664-1
CLR External clearance#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER1_SF1_SF1_SF2_SF1 Side 1 to side 2 distance through air >4 mm
CPG External creepage#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER1_SF1_SF1_SF2_SF1 Side 1 to side 2 distance across package surface >4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >400 V
Material Group According to IEC 60664-1 II
Overvoltage category Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER2_SF1_SF1_SF2_SF1
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 637 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test. See GUID-3733BCAC-9FBF-4D8D-9F2E-6002D22063AB.html#T4174073-12 450 VRMS
DC voltage 637 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 4242 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-us waveform per IEC 62368-1 5000 VPK
VIOSM Maximum surge isolation voltage(4) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),
1.2/50-μs waveform per IEC 62368-1		 6500 VPK
qpd Apparent charge#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER4_SF1_SF1_SF2_SF1 Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 × VIORM , tm = 10 s ≤ 5
Method b: At routine test (100% production) and preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.5 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)		 ≤ 5
CIO Barrier capacitance, input to output#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER5_SF1_SF1_SF2_SF1 VIO = 0.4 × sin (2 πft), f = 1 MHz ~0.5 pF
RIO Insulation resistance, input to output#A_ISO104X_ISOLATIONSPECS_INSULATION_SPECS_FOOTER5_SF1_SF1_SF2_SF1 VIO = 500 V,  TA = 25°C > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at  TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO672x is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.