8.1 Overview

The isolator in Figure 20 is based on a capacitive, isolation-barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Package Insulation and Safety-Related Specifications

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
L(I01)	Minimum air gap (Clearance)	Shortest terminal to terminal distance through air		8			mm
L(I02)(1)	Minimum external tracking (Creepage)	Shortest terminal to terminal distance across the package surface		8			mm
CTI	Tracking resistance (Comparative Tracking Index)	DIN EN 60112 (VDE 0303-11); IEC 60112		≥400			V
DTI	Minimum Internal Gap (Internal Clearance)	Distance through the insulation		0.014			mm
CI(2)	Input capacitance	VI = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V			2		pF

(1) Per JEDEC package dimensions.

(2) Measured from input pin to ground.

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NOTE

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.

Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

Table 1. DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics⁽¹⁾

PARAMETER		TEST CONDITIONS	SPECIFICATION	UNIT
VIORM	Maximum working insulation voltage		1414	VPEAK
VPR	Input-to-output test voltage	After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC	1697	VPEAK
		Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC	2262
		Method b1, 100% Production test VPR = VIORM x 1.875, t = 1 s Partial discharge < 5 pC	2652
VIOTM	Maximum transient overvoltage	VTEST = VIOTM t = 60 sec (Qualification) t = 1 sec (100% Production)	4242	VPEAK
RIO (2)	Isolation resistance, Input to Output	VIO = 500 V, TA = 25°C	>1012	Ω
		VIO = 500 V, 100°C ≤ TA ≤ 125°C	>1011
		VIO = 500 V at TS = 150°C	>109
CIO (2)	Barrier capacitance, Input to Output	VI = 0.4 sin (2πft), f = 1MHz	2	pF
	Pollution degree		2

(1) Climatic Classification 40/125/21

(2) All pins on each side of the barrier tied together creating a two-terminal device.

Table 2. IEC 60664-1 Ratings Table

PARAMETER	TEST CONDITIONS	SPECIFICATION
Material Group		II
Installation classification / Overvoltage category for basic insulation	Rated mains voltage ≤ 300 VRMS	I–IV
	Rated mains voltage ≤ 600 VRMS	I–III
	Rated mains voltage ≤ 1000 VRMS	I–II

Table 3. Regulatory Information

VDE	TUV	CSA	UL	CQC
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07	Certified according to EN/UL/CSA 60950-1 and 61010-1	Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1	Recognized under 1577 Component Recognition Program	Certified according to GB4943.1-2011
Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Working Voltage, 1414 VPK	3000 VRMS Reinforced Insulation, 400 VRMS maximum working voltage 3000 VRMS Basic Insulation, 600 VRMS maximum working voltage	3000 VRMS Isolation Rating	Single Protection, 2500 VRMS(1)	Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS Maximum Working Voltage
Certificate number: 40016131	Certificate number: U8V 13 09 77311 010	Master contract number: 220991	File number: E181974	Certificate number: CQC14001109542

(1) Production tested ≥ 3000 V_RMS for 1 second in accordance with UL 1577.

8.3.1.1 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
IS	Safety input, output, or supply current	DW-16	θJA = 77.5 °C/W, VI = 5.5V, TJ = 150°C, TA = 25°C			293	mA
			θJA = 77.5 °C/W, VI = 3.6V, TJ = 150°C, TA = 25°C			448
			θJA = 77.5 °C/W, VI = 2.7V, TJ = 150°C, TA = 25°C			597
TS	Maximum safety temperature					150	°C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

Figure 22. Thermal Derating Curve for Safety Limiting Current per VDE

8.4 Device Functional Modes

Figure 23. Device I/O Schematics