SLLSFK3 november   2022 ISOW7741-Q1 , ISOW7742-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics - Power Converter
    10. 7.10 Supply Current Characteristics - Power Converter
    11. 7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
    12. 7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
    13. 7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    14. 7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    15. 7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    16. 7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    17. 7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    18. 7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    19. 7.19 Switching Characteristics - 5-V Supply
    20. 7.20 Switching Characteristics - 3.3-V Supply
    21. 7.21 Switching Characteristics - 2.5-V Supply
    22. 7.22 Switching Characteristics - 1.8-V Supply
    23. 7.23 Insulation Characteristics Curves
    24. 7.24 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Power Isolation
      2. 9.1.2 Signal Isolation
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Power-Up and Power-Down Behavior
      3. 9.3.3 Protection Features
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
      4. 10.2.4 Insulation Lifetime
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electromagnetic Compatibility (EMC) Considerations

The ISOW7741-Q1 and ISOW7742-Q1 devices use emissions reduction schemes for the internal oscillator and advanced internal layout scheme to minimize radiated emissions at the system level.

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISOW7741-Q1 and ISOW7742-Q1 devices incorporate many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
  • Power path and signal path separated to minimize internal high frequency coupling and allowing for an external filtering knob using ferrite beads available to further reduce emissions

  • Reduced power converter switching frequency to 25 Mhz to reduce strength of high frequency components in emissions spectrum