SNOSD15B December   2016  – April 2017 LDC2112 , LDC2114

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Digital Interface
    7. 6.7 I2C Interface
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Multi-Channel and Single-Channel Operation
      2. 7.3.2 Button Output Interfaces
      3. 7.3.3 Programmable Button Sensitivity
      4. 7.3.4 Baseline Tracking
      5. 7.3.5 Integrated Button Algorithms
      6. 7.3.6 I2C Interface
        1. 7.3.6.1 Selectable I2C Address (LDC2112 Only)
        2. 7.3.6.2 I2C Interface Specifications
        3. 7.3.6.3 I2C Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Power Mode
      2. 7.4.2 Low Power Mode
      3. 7.4.3 Configuration Mode
    5. 7.5 Register Maps
      1. 7.5.1 Individual Register Listings
        1. 7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Theory of Operation
      2. 8.1.2  Designing Sensor Parameters
      3. 8.1.3  Setting COM Pin Capacitor
      4. 8.1.4  Defining Power-On Timing
      5. 8.1.5  Configuring Button Scan Rate
      6. 8.1.6  Programming Button Sampling Window
      7. 8.1.7  Scaling Frequency Counter Output
      8. 8.1.8  Setting Button Triggering Threshold
      9. 8.1.9  Tracking Baseline
      10. 8.1.10 Mitigating False Button Detections
        1. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common)
        2. 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)
        3. 8.1.10.3 Overcoming Case Twisting (Anti-Twist)
        4. 8.1.10.4 Mitigating Metal Deformation (Anti-Deform)
      11. 8.1.11 Reporting Interrupts for Button Presses and Error Conditions
      12. 8.1.12 Estimating Supply Current
    2. 8.2 Typical Application
      1. 8.2.1 Touch Button Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DSBGA Light Sensitivity
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The LDC2112/LDC2114 is a multi-channel, low-noise, high-resolution inductance to digital converter (LDC) optimized for inductive touch applications. Button presses form micro-deflections in the conductive targets which cause frequency shifts in the resonant sensors. The LDC2112/LDC2114 can measure such frequency shifts and determine when button presses have occurred. With adjustable sensitivity per input channel, the LDC2112/LDC2114 can reliably operate with a wide range of physical button structures and materials. The high resolution measurement enables the implementation of force level buttons. The LDC2112/LDC2114 incorporates customizable post-processing algorithms for enhanced robustness.

The LDC2112/LDC2114 can operate in an ultra-low power mode for optimal battery life, or can be toggled into a higher scan rate for more responsive button press detection for game play or other low latency applications. The LDC2112/LDC2114 is operational from –40 °C to +85 °C with a 1.8 V ± 5% power supply voltage.

The LDC2112/LDC2114 is configured through 400 kHz I2C. Button presses can be reported through the I2C interface or with configurable polarity dedicated push-pull outputs. Besides the LC resonant sensors, the only external components necessary for operation are supply bypassing capacitors and a COM pin capacitor to ground.

Functional Block Diagram

LDC2112 LDC2114 ldc2114-simplified-schematic-ldc2112-version-snosd15.gif Figure 10. Block Diagram of LDC2112
LDC2112 LDC2114 ldc2114-simplified-schematic-ldc2114-version-snosd15.gif Figure 11. Block Diagram of LDC2114

Feature Description

Multi-Channel and Single-Channel Operation

The LDC2112 provides two independent sensing channels; the LDC2114 provides four independent sensing channels. In the following sections, some parameters, such as DATAn and SENSORn_CONFIG, contain a channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114.

The LDC2112's two available channels are always enabled in Normal Power Mode. The LDC2112 sequentially samples both channels at the configured scan rate. Either channel can be independently enabled in Low Power Mode by setting the LPENn (n = 0 or 1) bit fields in Register EN (Address 0x0C).

Any of the LDC2114’s four available channels can be independently enabled by setting the ENn and LPENn (n = 0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect if the corresponding ENn bit is also set. If only one channel is set active, the LDC2114 periodically samples the single active channel at the configured scan rate. When several channels are set active, the LDC2114 operates in multi-channel mode, and it sequentially samples the active channels at the configured scan rate. Each channel of the LDC2114 can be independently enabled in Low Power Mode and Normal Power Mode.

Button Output Interfaces

Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2, or 3), which are push-pull outputs and can be used as interrupts to a micro-controller. The polarities of these pins are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also reported by the push-pull interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address 0x11). Any assertion of INTB is cleared upon reading Register STATUS (Address 0x00). Each push-pull output must be assigned to a dedicated general-purpose input pin on the micro-controller to avoid potential current fights.

The second method is by use of the LDC2112/LDC2114’s I2C interface. The Register OUT (Address 0x01) contains the fields OUT0, OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For more advanced button press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), which are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a micro-controller. A valid button push is represented by a positive value. The polarity is configurable in Register OPOL_DPOL (Address 0x1C). The DATAn values can be used to implement multi-level buttons, where the data value is correlated to the amount of force applied to the button.

Programmable Button Sensitivity

The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a 64-level gain factor for a normalized gain between 1 and 232. Each gain step increases the gain by an average of 9%.

The gain required for an application is primarily determined by the mechanical rigidity of each individual button. The individual gain steps are listed in the Gain Table.

Baseline Tracking

The LDC2112/LDC2114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the sensor output caused by environmental variations, such as temperature drift. The baseline tracking is configured independently for Normal Power Mode and Low Power Mode. For more information, refer to Tracking Baseline.

Integrated Button Algorithms

The LDC2112/LDC2114 features several algorithms that can mitigate false button detections due to mechanical non-idealities. The algorithms look for correlated button responses, for example, similar or opposite responses between two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more information, refer to Mitigating False Button Detections.

I2C Interface

The LDC2112/LDC2114 features an I2C Interface that can be used to program the internal registers and read channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x05) registers, the user should always read Register STATUS (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.

For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The sequence of register write is illustrated as follows:

After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above process is shown in Figure 12.

LDC2112 LDC2114 ldc2114-timing-diagram-representing-the-states-for-i2c-write-handshake-snosd15.gif Figure 12. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an I2C Write Handshake

Selectable I2C Address (LDC2112 Only)

The LDC2112 provides an I2C address select pin, ADDR. Connecting this pin to ground will set the LDC2112 I2C address to 0x2A. Connecting ADDR to VDD will set the LDC2112 I2C address to 0x2B.

The LDC2114 has a fixed I2C address of 0x2A.

I2C Interface Specifications

The maximum speed of the I2C interface is 400 kHz. This sequence uses the standard I2C 7-bit slave address followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will auto-increment as long as the master acknowledges.

LDC2112 LDC2114 ldc2114-i2c-sequence-of-writing-a-single-register-snosd15.gif Figure 13. I2C Sequence of Writing a Single Register
LDC2112 LDC2114 ldc2114-i2c-sequence-of-writing-consecutive-registers-snosd15.gif Figure 14. I2C Sequence of Writing Consecutive Registers
LDC2112 LDC2114 ldc2114-i2c-sequence-of-reading-a-single-register-snosd15.gif Figure 15. I2C Sequence of Reading a Single Register
LDC2112 LDC2114 ldc2114-i2c-sequence-of-reading-consecutive-registers-snosd15.gif Figure 16. I2C Sequence of Reading Consecutive Registers

I2C Bus Control

The LDC2112/LDC2114 cannot drive the I2C clock (SCL), i.e. it does not support clock stretching. In the unlikely event where the SCL is stuck LOW, power cycle any device that is holding the SCL to activate its internal Power-On Reset (POR) circuit. If the LDC is connected to the same power supply as that device, there will be about 66 ms set-up time before the LDC becomes active again. For more information, refer to Defining Power-On Timing. If the data line (SDA) is stuck LOW, the I2C master should send nine clock pulses. The device that is holding the bus LOW should release it sometime within those nine clocks. If not, then power cycle to clear the bus.

The LDC2112/LDC2114 has built-in monitors to check that the device is currently working. In the unlikely event of a device fault, the device state will be reset internally, and all the registers will be reset with default settings. For system robustness, it is recommended to check the value of a modified register periodically to monitor the device status and reload the register settings if needed.

Device Functional Modes

The LDC2112/LDC2114 supports two power modes of operation, a Normal Power Mode for active sampling at 10, 20, 40, or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS. Refer to Configuring Button Scan Rate for details.

Normal Power Mode

When the LPWRB input pin is set to VDD, all enabled channels operate in Normal Power Mode. Each channel can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal Power Mode Scan Rate, refer to Electrical Characteristics.

Low Power Mode

When the LPWRB input pin is set to Ground, only the low-power-enabled channels are active. Each channel can be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel to operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive power-saving state for the majority of the time. Lower scan rates correspond to lower current consumption. In addition, the individual button sampling window should be set to the lowest effective setting (this is system dependent, but typically 0.8 to 1 ms). For the electrical specification of the configurable Low Power Mode Scan Rate, refer to Electrical Characteristics.

If a channel is operational in both Low Power Mode and Normal Power Mode, it is recommended to toggle the LPWRB pin only after the button associated with that channel is released.

Configuration Mode

Before configuring any register settings, the device must be put into the configuration mode first. Setting CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device in configuration mode. Any device configuration changes can then be made. The current consumption in this mode is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation. Refer to I2C Interface for more information.

Register Maps

Registers indicated with Reserved must be written only with indicated values. Improper device operation may occur otherwise.

Table 1. Register List

ADDRESS NAME DEFAULT VALUE DESCRIPTION
0x00 STATUS 0x00 Device status
0x01 OUT 0x00 Channel output logic states
0x02 DATA0_LSB 0x00 The lower 8 bits of the Button 0 data (Two’s complement)
0x03 DATA0_MSB 0x00 The upper 4 bits of the Button 0 data (Two’s complement)
0x04 DATA1_LSB 0x00 The lower 8 bits of the Button 1 data (Two’s complement)
0x05 DATA1_MSB 0x00 The upper 4 bits of the Button 1 data (Two’s complement)
0x06 DATA2_LSB 0x00 The lower 8 bits of the Button 2 data (Two’s complement)
0x07 DATA2_MSB 0x00 The upper 4 bits of the Button 2 data (Two’s complement)
0x08 DATA3_LSB 0x00 The lower 8 bits of the Button 3 data (Two’s complement)
0x09 DATA3_MSB 0x00 The upper 4 bits of the Button 3 data (Two’s complement)
0x0A RESET 0x00 Reset device and register configurations
0x0B RESERVED 0x00 Reserved. Set to 0x00
0x0C EN 0x10 (LDC2112)
0x1F (LDC2114)
Enable channels and low power modes
0x0D NP_SCAN_RATE 0x01 Normal Power Mode scan rate
0x0E GAIN0 0x28 Gain for Channel 0 sensitivity adjustment
0x0F LP_SCAN_RATE 0x02 Low Power Mode scan rate
0x10 GAIN1 0x28 Gain for Channel 1 sensitivity adjustment
0x11 INTPOL 0x01 Interrupt polarity
0x12 GAIN2 0x28 Gain for Channel 2 sensitivity adjustment
0x13 LP_BASE_INC 0x05 Low power base increment
0x14 GAIN3 0x28 Gain for Channel 3 sensitivity adjustment
0x15 NP_BASE_INC 0x03 Normal power base increment
0x16 BTPAUSE_MAXWIN 0x00 Baseline tracking pause and Max-win
0x17 LC_DIVIDER 0x03 LC oscillation frequency divider
0x18 HYST 0x08 Hysteresis for threshold
0x19 TWIST 0x00 Anti-twist
0x1A COMMON_DEFORM 0x00 Anti-common and anti-deformation
0x1B RESERVED 0x00 Reserved. Set to 0x00
0x1C OPOL_DPOL 0x0F Output polarity
0x1D RESERVED 0x00 Reserved. Set to 0x00
0x1E CNTSC 0x55 Counter scale
0x1F RESERVED 0x00 Reserved. Set to 0x00
0x20 SENSOR0_CONFIG 0x04 Sensor 0 cycle count, frequency, RP range
0x21 RESERVED 0x00 Reserved. Set to 0x00
0x22 SENSOR1_CONFIG 0x04 Sensor 1 cycle count, frequency, RP range
0x23 RESERVED 0x00 Reserved. Set to 0x00
0x24 SENSOR2_CONFIG 0x04 Sensor 2 cycle count, frequency, RP range
0x25 FTF0 0x02 Sensor 0 fast tracking factor
0x26 SENSOR3_CONFIG 0x04 Sensor 3 cycle count, frequency, RP range
0x27 RESERVED 0x00 Reserved. Set to 0x00
0x28 FTF1_2 0x50 Sensors 1 and 2 fast tracking factors
0x29 RESERVED 0x00 Reserved. Set to 0x00
0x2A RESERVED 0x00 Reserved. Set to 0x00
0x2B FTF3 0x01 Sensor 3 fast tracking factor
0xFC MANUFACTURER_ID_LSB 0x49 Manufacturer ID lower byte
0xFD MANUFACTURER_ID_MSB 0x54 Manufacturer ID upper byte
0xFE DEVICE_ID_LSB 0x01 (LDC2112)
0x00 (LDC2114)
Device ID lower byte
0xFF DEVICE_ID_MSB 0x20 Device ID upper byte

Individual Register Listings

Fields indicated with ‘Reserved’ must be written only with indicated values. Improper device operation may occur otherwise. The R/W column indicates the Read-Write status of the corresponding field. An ‘R/W’ entry indicates read and write capability, an ‘R’ indicates read-only, and a ‘W’ indicates write-only.

Before reading the OUT (Address 0x01) or channel DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), the user should always read the STATUS register (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.

Table 2. Register STATUS – Address 0x00

BIT FIELD TYPE RESET DESCRIPTION
7 OUT_STATUS R 0 Output Status
Logic OR of output bits from Register OUT (Address 0x01). This field is cleared by reading this register.
6 CHIP_READY R 1 Chip Ready Status
b0: Chip not ready after internal reset.
b1: Chip ready after internal reset.
5 RDY_TO_WRITE R 0 Ready to Write
Indicates if registers are ready to be written. See I2C Interface for more information.
b0: Registers not ready.
b1: Registers ready.
4 MAXOUT R 0 Maximum Output Code
Indicates if any channel output data reaches the maximum value (+0x7FF or –0x800). Cleared by a read of the status register.
b0: No maximum output code.
b1: Maximum output code.
3 FSM_WD R 0 Finite-State Machine Watchdog Error
Reports an error has occurred and conversions have been halted. Cleared by a read of the status register.
b0: No error in finite-state machine.
b1: Error in finite-state machine.
2 LC_WD R 0 LC Sensor Watchdog Error
Reports an error when any LC oscillator fails to start. Cleared by a read of the status register.
b0: No error in LC oscillator initialization.
b1: Error in LC oscillator initialization.
1 TIMEOUT R 0 Button Timeout
Reports when any button is asserted for more than 50 seconds. Cleared by a read of the status register.
b0: no timeout error.
b1: timeout error.
0 REGISTER_FLAG R 0 Register Integrity Flag
Reports if any register's value has an unexpected change. Cleared by a read of the status register.
b0: No unexpected register change.
b1: Unexpected register change.

Table 3. Register OUT – Address 0x01

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R 0000 Reserved. Set to b0000.
3 OUT3 R 0 Output Logic State for Channel 3 (LDC2114 Only)
b0: No button press detected on Channel 3.
b1: Button press detected on Channel 3.
2 OUT2 R 0 Output Logic State for Channel 2 (LDC2114 Only)
b0: No button press detected on Channel 2.
b1: Button press detected on Channel 2.
1 OUT1 R 0 Output Logic State for Channel 1
b0: No button press detected on Channel 1.
b1: Button press detected on Channel 1.
0 OUT0 R 0 Output Logic State for Channel 0
b0: No button press detected on Channel 0.
b1: Button press detected on Channel 0.

Table 4. Register DATA0_LSB – Address 0x02

BIT FIELD TYPE RESET DESCRIPTION
7:0 DATA0[7:0] R 0000 0000 The lower 8 bits of Channel 0 data (Two’s complement).

Table 5. Register DATA0_MSB – Address 0x03

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R 0000 Reserved.
3:0 DATA0[11:8] R 0000 The upper 4 bits of Channel 0 data (Two’s complement).

Table 6. Register DATA1_LSB – Address 0x04

BIT FIELD TYPE RESET DESCRIPTION
7:0 DATA1[7:0] R 0000 0000 The lower 8 bits of Channel 1 data (Two’s complement).

Table 7. Register DATA1_MSB – Address 0x05

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R 0000 Reserved.
3:0 DATA1[11:8] R 0000 The upper 4 bits of Channel 1 data (Two’s complement).

Table 8. Register DATA2_LSB – Address 0x06

BIT FIELD TYPE RESET DESCRIPTION
7:0 DATA2[7:0] R 0000 0000 The lower 8 bits of Channel 2 data (Two’s complement).
(LDC2114 Only)

Table 9. Register DATA2_MSB – Address 0x07

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R 0000 Reserved.
3:0 DATA2[11:8] R 0000 The upper 4 bits of Channel 2 data (Two’s complement).
(LDC2114 Only)

Table 10. Register DATA3_LSB – Address 0x08

BIT FIELD TYPE RESET DESCRIPTION
7:0 DATA3[7:0] R 0000 0000 The lower 8 bits of Channel 3 data (Two’s complement).
(LDC2114 Only)

Table 11. Register DATA3_MSB – Address 0x09

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R 0000 Reserved.
3:0 DATA3[11:8] R 0000 The upper 4 bits of Channel 3 data (Two’s complement).
(LDC2114 Only)

Table 12. Register RESET – Address 0x0A

BIT FIELD TYPE RESET DESCRIPTION
7:5 RESERVED R/W 000 Reserved. Set to b000.
4 FULL_RESET R/W 0 Device Reset
b0: Normal operation.
b1: Resets the device and register configurations. All registers will be returned to default values. Normal operation will not resume until STATUS:CHIP_READY = 1.
3:1 RESERVED R/W 000 Reserved. Set to b000.
0 CONFIG_MODE R/W 0 Configuration Mode
b0: Normal operation.
b1: Holds the device in configuration mode (no data conversion), but maintains current register configurations. Any device configuration changes should be made with this bit set to 1. After all configuration changes have been written, set this bit to 0 for normal operation.

Table 13. Register EN – Address 0x0C

BIT FIELD TYPE RESET DESCRIPTION
7 LPEN3 R/W 0 Channel 3 Low-Power-Enable (LDC2114 Only)
b0: Disable Channel 3 in Low Power Mode.
b1: Enable Channel 3 in Low Power Mode. EN3 must also be set to 1.
6 LPEN2 R/W 0 Channel 2 Low-Power-Enable (LDC2114 Only)
b0: Disable Channel 2 in Low Power Mode.
b1: Enable Channel 2 in Low Power Mode. EN2 must also be set to 1.
5 LPEN1 R/W 0 Channel 1 Low-Power-Enable
b0: Disable Channel 1 in Low Power Mode.
b1: Enable Channel 1 in Low Power Mode. EN1 must also be set to 1.
4 LPEN0 R/W 1 Channel 0 Low-Power-Enable
b0: Disable Channel 0 in Low Power Mode.
b1: Enable Channel 0 in Low Power Mode. EN0 must also be set to 1.
3 EN3 (LDC2114) R/W 1 Channel 3 Enable (LDC2114 Only)
b0: Disable Channel 3.
b1: Enable Channel 3.
RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only)
2 EN2 (LDC2114) R/W 1 Channel 2 Enable (LDC2114 Only)
b0: Disable Channel 2.
b1: Enable Channel 2.
RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only)
1 EN1 (LDC2114) R/W 1 Channel 1 Enable (LDC2114 Only)
b0: Disable Channel 1.
b1: Enable Channel 1.
RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only)
For LDC2112, Channel 1 is always enabled.
0 EN0 (LDC2114) R/W 1 Channel 0 Enable (LDC2114 Only)
b0: Disable Channel 0.
b1: Enable Channel 0.
RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only)
For LDC2112, Channel 0 is always enabled.

Table 14. Register NP_SCAN_RATE – Address 0x0D

BIT FIELD TYPE RESET DESCRIPTION
7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000.
1:0 NPSR R/W 01 Normal Power Mode Scan Rate
Refer to Configuring Button Scan Rate for more information.
b00: 80 SPS
b01: 40 SPS (Default)
b10: 20 SPS
b11: 10 SPS

Table 15. Register GAIN0 – Address 0x0E

BIT FIELD TYPE RESET DESCRIPTION
7:6 RESERVED R/W 00 Reserved. Set to b00.
5:0 GAIN0 R/W b10 1000 Gain for Channel 0
Refer to the Gain Table for detailed configuration.

Table 16. Register LP_SCAN_RATE – Address 0x0F

BIT FIELD TYPE RESET DESCRIPTION
7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000.
1:0 LPSR R/W 10 Low Power Mode Scan Rate
Refer to Configuring Button Scan Rate for more information.
b00: 5 SPS
b01: 2.5 SPS
b10: 1.25 SPS (Default)
b11: 0.625 SPS

Table 17. Register GAIN1 – Address 0x10

BIT FIELD TYPE RESET DESCRIPTION
7:6 RESERVED R/W 00 Reserved. Set to b00.
5:0 GAIN1 R/W b10 1000 Gain for Channel 1
Refer to the Gain Table for detailed configuration.

Table 18. Register INTPOL – Address 0x11

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2 INTPOL R/W 0 Interrupt Polarity
b0: Set INTB pin polarity to active low.
b1: Set INTB pin polarity to active high.
1:0 RESERVED R/W 01 Reserved. Set to b01.

Table 19. Register GAIN2 – Address 0x12

BIT FIELD TYPE RESET DESCRIPTION
7:6 RESERVED R/W 00 Reserved. Set to b00.
5:0 GAIN2 R/W b10 1000 Gain for Channel 2 (LDC2114 Only)
Refer to the Gain Table for detailed configuration.

Table 20. Register LP_BASE_INC – Address 0x13

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2:0 LPBI R/W b101 Baseline Tracking Increment in Low Power Mode
Refer to Tracking Baseline for more information. Valid values: [b000:b111].
b101: LPBI = 5 (Default)

Table 21. Register GAIN3 – Address 0x14

BIT FIELD TYPE RESET DESCRIPTION
7:6 RESERVED R/W 00 Reserved. Set to b00.
5:0 GAIN3 R/W b10 1000 Gain for Channel 3 (LDC2114 Only)
Refer to the Gain Table for detailed configuration.

Table 22. Register NP_BASE_INC – Address 0x15

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2:0 NPBI R/W b011 Baseline Tracking Increment in Normal Power Mode
Refer to Tracking Baseline for more information. Valid values: [b000:b111].
b011: NPBI = 3 (Default)

Table 23. Register BTPAUSE_MAXWIN – Address 0x16

BIT FIELD TYPE RESET DESCRIPTION
7 BTPAUSE3 R/W 0 Baseline Tracking Pause for Channel 3 (LDC2114 Only)
Pauses baseline tracking for Channel 3 when OUT3 is asserted. Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 3 regardless of OUT3 status. (Default)
b1: Pauses baseline tracking for Channel 3 when OUT3 is asserted.
6 BTPAUSE2 R/W 0 Baseline Tracking Pause for Channel 2 (LDC2114 Only)
Pauses baseline tracking for Channel 2 when OUT2 is asserted. Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 2 regardless of OUT2 status. (Default)
b1: Pauses baseline tracking for Channel 2 when OUT2 is asserted.
5 BTPAUSE1 R/W 0 Baseline Tracking Pause for Channel 1
Pauses baseline tracking for Channel 1 when OUT1 is asserted. Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 1 regardless of OUT1 status. (Default)
b1: Pauses baseline tracking for Channel 1 when OUT1 is asserted.
4 BTPAUSE0 R/W 0 Baseline Tracking Pause for Channel 0
Pauses baseline tracking for Channel 0 when OUT0 is asserted. Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 0 regardless of OUT0 status. (Default)
b1: Pauses baseline tracking for Channel 0 when OUT0 is asserted.
3 MAXWIN3 R/W 0 Max-Win Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Resolving Simultaneous Button Presses (Max-Win) for more information.
b0: Exclude Channel 3 from the max-win group. (Default)
b1: Include Channel 3 in the max-win group.
2 MAXWIN2 R/W 0 Max-Win Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Resolving Simultaneous Button Presses (Max-Win) for more information.
b0: Exclude Channel 2 from the max-win group. (Default)
b1: Include Channel 2 in the max-win group.
1 MAXWIN1 R/W 0 Max-Win Algorithm Setting for Channel 1
Refer to Resolving Simultaneous Button Presses (Max-Win) for more information.
b0: Exclude Channel 1 from the max-win group. (Default)
b1: Include Channel 1 in the max-win group.
0 MAXWIN0 R/W 0 Max-Win Algorithm Setting for Channel 0
Refer to Resolving Simultaneous Button Presses (Max-Win) for more information.
b0: Exclude Channel 0 from the max-win group. (Default)
b1: Include Channel 0 in the max-win group.

Table 24. Register LC_DIVIDER – Address 0x17

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2:0 LCDIV R/W b011 LC Oscillation Frequency Divider
The frequency divider sets the button sampling window in conjunction with SENCYCn. Valid values: [b000:b111].
Refer to Programming Button Sampling Window for more information.
b011: LCDIV = 3 (Default)

Table 25. Register HYST – Address 0x18

BIT FIELD TYPE RESET DESCRIPTION
7:4 RESERVED R/W b0000 Reserved. Set to b0000.
3:0 HYST R/W b1000 Hysteresis
Defines the hysteresis for button triggering threshold. Valid values: [b0000:b1111].
Hysteresis = HYST × 4
b1000: HYST = 8, Hysteresis = 32 (Default)
Refer to Setting Button Triggering Threshold for more information.

Table 26. Register TWIST – Address 0x19

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2:0 ANTITWIST R/W b000 Anti-Twist
When set to 0, the anti-twist algorithm is not enabled.
When greater than 0, all buttons are enabled for the anti-twist algorithm. The validation of all buttons is void if any button’s DATA is negative by a threshold.
Anti-twist Threshold = ANTITWIST × 4.
Refer to Overcoming Case Twisting (Anti-Twist) for more information.

Table 27. Register COMMON_DEFORM – Address 0x1A

BIT FIELD TYPE RESET DESCRIPTION
7 ANTICOM3 R/W 0 Anti-Common Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Eliminating Common-Mode Change (Anti-Common) for more information.
b0: Exclude Channel 3 from the anti-common group. (Default)
b1: Include Channel 3 in the anti-common group.
6 ANTICOM2 R/W 0 Anti-Common Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Eliminating Common-Mode Change (Anti-Common) for more information.
b0: Exclude Channel 2 from the anti-common group. (Default)
b1: Include Channel 2 in the anti-common group.
5 ANTICOM1 R/W 0 Anti-Common Algorithm Setting for Channel 1
Refer to Eliminating Common-Mode Change (Anti-Common) for more information.
b0: Exclude Channel 1 from the anti-common group. (Default)
b1: Include Channel 1 in the anti-common group.
4 ANTICOM0 R/W 0 Anti-Common Algorithm Setting for Channel 0
Refer to Eliminating Common-Mode Change (Anti-Common) for more information.
b0: Exclude Channel 0 from the anti-common group. (Default)
b1: Include Channel 0 in the anti-common group.
3 ANTIDFORM3 R/W 0 Anti-Deform Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Mitigating Metal Deformation (Anti-Deform) for more information.
b0: Exclude Channel 3 from the anti-deform group. (Default)
b1: Include Channel 3 in the anti-deform group.
2 ANTIDFORM2 R/W 0 Anti-Deform Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Mitigating Metal Deformation (Anti-Deform) for more information.
b0: Exclude Channel 2 from the anti-deform group. (Default)
b1: Include Channel 2 in the anti-deform group.
1 ANTIDFORM1 R/W 0 Anti-Deform Algorithm Setting for Channel 1
Refer to Mitigating Metal Deformation (Anti-Deform) for more information.
b0: Exclude Channel 1 from the anti-deform group. (Default)
b1: Include Channel 1 in the anti-deform group.
0 ANTIDFORM0 R/W 0 Anti-Deform Algorithm Setting for Channel 0
Refer to Mitigating Metal Deformation (Anti-Deform) for more information.
b0: Exclude Channel 0 from the anti-deform group. (Default)
b1: Include Channel 0 in the anti-deform group.

Table 28. Register OPOL_DPOL – Address 0x1C

BIT FIELD TYPE RESET DESCRIPTION
7 OPOL3 R/W 0 Output Polarity for OUT3 Pin (LDC2114 Only)
b0: Active low (Default)
b1: Active high
6 OPOL2 R/W 0 Output Polarity for OUT2 Pin (LDC2114 Only)
b0: Active low (Default)
b1: Active high
5 OPOL1 R/W 0 Output Polarity for OUT1 Pin
b0: Active low (Default)
b1: Active high
4 OPOL0 R/W 0 Output Polarity for OUT0 Pin
b0: Active low (Default)
b1: Active high
3 DPOL3 R/W 1 Data Polarity for Channel 3 (LDC2114 Only)
b0: DATA3 decreases as fSENSOR3 increases.
b1: DATA3 increases as fSENSOR3 increases. (Default)
2 DPOL2 R/W 1 Data Polarity for Channel 2 (LDC2114 Only)
b0: DATA2 decreases as fSENSOR2 increases.
b1: DATA2 increases as fSENSOR2 increases. (Default)
1 DPOL1 R/W 1 Data Polarity for Channel 1
b0: DATA1 decreases as fSENSOR1 increases.
b1: DATA1 increases as fSENSOR1 increases. (Default)
0 DPOL0 R/W 1 Data Polarity for Channel 0
b0: DATA0 decreases as fSENSOR0 increases.
b1: DATA0 increases as fSENSOR0 increases. (Default)

Table 29. Register CNTSC – Address 0x1E(1)

BIT FIELD TYPE RESET DESCRIPTION
7:6 CNTSC3 R/W 01 Counter Scale for Channel 3 (LDC2114 Only)
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC3 = 0
b01: CNTSC3 = 1 (Default)
b10: CNTSC3 = 2
b11: CNTSC3 = 3
5:4 CNTSC2 R/W 01 Counter Scale for Channel 2 (LDC2114 Only)
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC2 = 0
b01: CNTSC2 = 1 (Default)
b10: CNTSC2 = 2
b11: CNTSC2 = 3
3:2 CNTSC1 R/W 01 Counter Scale for Channel 1
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC1 = 0
b01: CNTSC1 = 1 (Default)
b10: CNTSC1 = 2
b11: CNTSC1 = 3
1:0 CNTSC0 R/W 01 Counter Scale for Channel 0
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC0 = 0
b01: CNTSC0 = 1 (Default)
b10: CNTSC0 = 2
b11: CNTSC0 = 3
The Counter Scale sets a scaling factor for the internal frequency counter to avoid data overflow. The formula for calculating counter scale is CNTSCn = LCDIV + ceiling(log2 (0.0861×(SENCYCn+1)/fSENSORn)), n = 0, 1, 2, or 3, where LCDIV and SENCYCn are the exponential and linear scalers that set the number of sensor oscillation cycles, fSENSORn is the sensor frequency in MHz.

Table 30. Register SENSOR0_CONFIG – Address 0x20

BIT FIELD TYPE RESET DESCRIPTION
7 RP0 R/W 0 Channel 0 Sensor RP Range Select
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350Ω ≤ RP ≤ 4kΩ (Default)
b1: 800Ω ≤ RP ≤ 10kΩ
6:5 FREQ0 R/W 00 Channel 0 Sensor Frequency Range Select
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
4:0 SENCYC0 R/W b0 0100 Channel 0 Sensor Cycle Count
SENCYC0 sets the Channel 0 button sampling window in conjunction with LCDIV.
Refer to Programming Button Sampling Window for more information.

Table 31. Register SENSOR1_CONFIG – Address 0x22

BIT FIELD TYPE RESET DESCRIPTION
7 RP1 R/W 0 Channel 1 Sensor RP Range Select
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5 FREQ1 R/W 00 Channel 1 Sensor Frequency Range Select
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
4:0 SENCYC1 R/W b0 0100 Channel 1 Sensor Cycle Count
SENCYC1 sets the Channel 1 button sampling window in conjunction with LCDIV.
Refer to Programming Button Sampling Window for more information.

Table 32. Register SENSOR2_CONFIG – Address 0x24

BIT FIELD TYPE RESET DESCRIPTION
7 RP2 R/W 0 Channel 2 Sensor RP Range Select (LDC2114 Only)
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5 FREQ2 R/W 00 Channel 2 Sensor Frequency Range Select (LDC2114 Only)
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
4:0 SENCYC2 R/W b0 0100 Channel 2 Sensor Cycle Count (LDC2114 Only)
SENCYC2 sets the Channel 2 button sampling window in conjunction with LCDIV.
Refer to Programming Button Sampling Window for more information.

Table 33. Register FTF0 – Address 0x25

BIT FIELD TYPE RESET DESCRIPTION
7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000.
2:1 FTF0 R/W 01 Fast Tracking Factor for Channel 0
Defines baseline tracking speed for negative values of DATA0.
Refer to Tracking Baseline for more information.
b00: FTF0 = 0
b01: FTF0 = 1 (Default)
b10: FTF0 = 2
b11: FTF0 = 3
0 RESERVED R/W 0 Reserved. Set to b0.

Table 34. Register SENSOR3_CONFIG – Address 0x26

BIT FIELD TYPE RESET DESCRIPTION
7 RP3 R/W 0 Channel 3 Sensor RP Range Select (LDC2114 Only)
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5 FREQ3 R/W 00 Channel 3 Sensor Frequency Range Select (LDC2114 Only)
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
4:0 SENCYC3 R/W b0 0100 Channel 3 Sensor Cycle Count (LDC2114 Only)
SENCYC3 sets the Channel 3 button sampling window in conjunction with LCDIV.
Refer to Programming Button Sampling Window for more information.

Table 35. Register FTF1_2 – Address 0x28

BIT FIELD TYPE RESET DESCRIPTION
7:6 FTF2 R/W 01 Fast Tracking Factor for Channel 2 (LDC2114 Only)
Defines baseline tracking speed for negative values of DATA2.
Refer to Tracking Baseline for more information.
b00: FTF2 = 0
b01: FTF2 = 1 (Default)
b10: FTF2 = 2
b11: FTF2 = 3
5:4 FTF1 R/W 01 Fast Tracking Factor for Channel 1
Defines baseline tracking speed for negative values of DATA1.
Refer to Tracking Baseline for more information.
b00: FTF1 = 0
b01: FTF1 = 1 (Default)
b10: FTF1 = 2
b11: FTF1 = 3
3:0 RESERVED R/W b0000 Reserved. Set to b0000.

Table 36. Register FTF3 – Address 0x2B

BIT FIELD TYPE RESET DESCRIPTION
7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000.
1:0 FTF3 R/W 01 Fast Tracking Factor for Channel 3 (LDC2114 Only)
Defines baseline tracking speed for negative values of DATA3.
Refer to Tracking Baseline for more information.
b00: FTF3 = 0
b01: FTF3 = 1 (Default)
b10: FTF3 = 2
b11: FTF3 = 3

Table 37. Register MANUFACTURER_ID_LSB – Address 0xFC

BIT FIELD TYPE RESET DESCRIPTION
7:0 MANUFACTURER_ID [7:0] R 0x49 Manufacturer ID [7:0]

Table 38. Register MANUFACTURER_ID_MSB – Address 0xFD

BIT FIELD TYPE RESET DESCRIPTION
7:0 MANUFACTURER_ID [15:8] R 0x54 Manufacturer ID [15:8]

Table 39. Register DEVICE_ID_LSB – Address 0xFE

BIT FIELD TYPE RESET DESCRIPTION
7:0 DEVICE_ID [7:0] R 0x01 (LDC2112) Device ID [7:0]
0x00 (LDC2114)

Table 40. Register DEVICE_ID_MSB – Address 0xFF

BIT FIELD TYPE RESET DESCRIPTION
7:0 DEVICE_ID [15:8] R 0x20 Device ID [15:8]

Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3

Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors

BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR
0 1.0 32 16
1 1.0625 33 17
2 1.1875 34 19
3 1.3125 35 21
4 1.4375 36 23
5 1.5625 37 25
6 1.6875 38 27
7 1.8125 39 29
8 2.0 40 32
9 2.125 41 34
10 2.375 42 38
11 2.625 43 42
12 2.875 44 46
13 3.125 45 50
14 3.375 46 54
15 3.625 47 58
16 4.0 48 64
17 4.25 49 68
18 4.75 50 76
19 5.25 51 84
20 5.75 52 92
21 6.25 53 100
22 6.75 54 108
23 7.25 55 116
24 8.0 56 128
25 8.5 57 136
26 9.5 58 152
27 10.5 59 168
28 11.5 60 184
29 12.5 61 200
30 13.5 62 216
31 14.5 63 232