SNVS700G December   2010  – October 2016 LM25066A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SMBus Communications
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
      2. 8.3.2 Circuit Breaker
      3. 8.3.3 Power Limit
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Overvoltage Lockout (OVLO)
      6. 8.3.6 Power Good
      7. 8.3.7 VDD Sub-Regulator
      8. 8.3.8 Remote Temperature Sensing
      9. 8.3.9 Damaged MOSFET Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Up Sequence
      2. 8.4.2 Gate Control
      3. 8.4.3 Fault Timer and Restart
      4. 8.4.4 Shutdown Control
      5. 8.4.5 Enabling/Disabling and Resetting
    5. 8.5 Register Maps
      1. 8.5.1 PMBus Command Support
        1. 8.5.1.1 Standard PMBus™ Commands
          1. 8.5.1.1.1  OPERATION (01h)
          2. 8.5.1.1.2  CLEAR_FAULTS (03h)
          3. 8.5.1.1.3  CAPABILITY (19h)
          4. 8.5.1.1.4  VOUT_UV_WARN_LIMIT (43h)
          5. 8.5.1.1.5  OT_FAULT_LIMIT (4Fh)
          6. 8.5.1.1.6  OT_WARN_LIMIT (51h)
          7. 8.5.1.1.7  VIN_OV_WARN_LIMIT (57h)
          8. 8.5.1.1.8  VIN_UV_WARN_LIMIT (58h)
          9. 8.5.1.1.9  STATUS_BYTE (78h)
          10. 8.5.1.1.10 STATUS_WORD (79h)
          11. 8.5.1.1.11 STATUS_VOUT (7Ah)
          12. 8.5.1.1.12 STATUS_INPUT (7Ch)
          13. 8.5.1.1.13 STATUS_TEMPERATURE (7Dh)
          14. 8.5.1.1.14 STATUS_CML (7Eh)
          15. 8.5.1.1.15 STATUS_MFR_SPECIFIC (80h)
          16. 8.5.1.1.16 READ_VIN (88h)
          17. 8.5.1.1.17 READ_VOUT (8Bh)
          18. 8.5.1.1.18 READ_TEMPERATURE_1 (8Dh)
          19. 8.5.1.1.19 MFR_ID (99h)
          20. 8.5.1.1.20 MFR_MODEL (9Ah)
          21. 8.5.1.1.21 MFR_REVISION (9Bh)
        2. 8.5.1.2 Manufacturer Specific PMBus™ Commands
          1. 8.5.1.2.1  MFR_SPECIFIC_00: READ_VAUX (D0h)
          2. 8.5.1.2.2  MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
          3. 8.5.1.2.3  MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
          4. 8.5.1.2.4  MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
          5. 8.5.1.2.5  MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
          6. 8.5.1.2.6  MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
          7. 8.5.1.2.7  MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
          8. 8.5.1.2.8  MFR_SPECIFIC_07: GATE_MASK (D7h)
          9. 8.5.1.2.9  MFR_SPECIFIC_08: ALERT_MASK (D8h)
          10. 8.5.1.2.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
          11. 8.5.1.2.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
          12. 8.5.1.2.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
          13. 8.5.1.2.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
          14. 8.5.1.2.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
          15. 8.5.1.2.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
          16. 8.5.1.2.16 MFR_SPECIFIC_15: READ_AVG_PIN (DFh)
          17. 8.5.1.2.17 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
          18. 8.5.1.2.18 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
          19. 8.5.1.2.19 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
        3. 8.5.1.3 Reading and Writing Telemetry Data and Warning Thresholds
        4. 8.5.1.4 Determining Telemetry Coefficients Empirically With Linear Fit
        5. 8.5.1.5 Writing Telemetry Data
        6. 8.5.1.6 PMBus™ Address Lines (ADR0, ADR1, ADR2)
        7. 8.5.1.7 SMBA Response
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 12-V, 45-A PMBus Hotswap Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Select RSNS and CL Setting
          2. 9.2.1.2.2  Selecting the Hotswap FETs
          3. 9.2.1.2.3  Select Power Limit
          4. 9.2.1.2.4  Set Fault Timer
          5. 9.2.1.2.5  Check MOSFET SOA
          6. 9.2.1.2.6  Switching to dV/dt based Start-up
          7. 9.2.1.2.7  Choosing the VOUT Slew Rate
          8. 9.2.1.2.8  Select Power Limit and Fault Timer
          9. 9.2.1.2.9  Set Undervoltage and Overvoltage Threshold
            1. 9.2.1.2.9.1 Option A
            2. 9.2.1.2.9.2 Option B
            3. 9.2.1.2.9.3 Option C
            4. 9.2.1.2.9.4 Option D
          10. 9.2.1.2.10 Power Good Pin
          11. 9.2.1.2.11 Input and Output Protection
          12. 9.2.1.2.12 Final Schematic and Component Values
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage VIN, SENSE to GND (2) –0.3 24 V
GATE, FB, UVLO/EN, OVLO, PGD to GND (2) –0.3 20 V
OUT to GND –1 20 V
SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND –0.3 6 V
VIN to SENSE –0.3 0.3 V
Junction Temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The GATE pin voltage is typically 7.5 V above VIN when the LM25066A is enabled. Therefore the Absolute Maximum Rating of 24 V for VIN and SENSE apply only when the LM25066A is disabled or for a momentary surge to that voltage since the Absolute Maximum Rating of the GATE pin is 20V.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM) (1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
The human body model is a 100-pF capacitor discharged through a 1.5 kΩ resistor into each pin.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN, SENSE, OUT voltage 2.9 17 V
VDD 2.9 5.5 V
Junction temperature, TJ –40 125 °C

Thermal Information

THERMAL METRIC(1) LM25066A UNIT
NHZ (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 34.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28.9 °C/W
RθJB Junction-to-board thermal resistance 13.4 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 13.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

Typical limits are for TJ = 25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to 85°C). Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V.(1)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (VIN PIN)
IIN-EN Input current, enabled UVLO = 2 V and OVLO = 0.7 V 5.8 8 mA
POR Power on reset threshold at VIN VIN increasing 2.6 2.8 V
PORHYS POREN hysteresis VIN decreasing 150 mV
VDD REGULATOR (VDD PIN)
VDD IVDD = 5 mA, VIN = 12 V 4.3 4.5 4.7 V
IVDD = 5 mA, VIN = 4.5 V 3.5 3.9 4.3 V
VDDILIM VDD current limit 25 45 mA
UVLO/EN, OVLO PINS
UVLOTH UVLO threshold VUVLO Falling 1.147 1.16 1.173 V
UVLOHYS UVLO hysteresis current UVLO = 1 V 18 23 28 µA
UVLODEL UVLO delay Delay to GATE high 8 µs
Delay to GATE low 20
UVLOBIAS UVLO bias current UVLO = 3 V 1 µA
OVLOTH OVLO threshold VOVLO rising 1.141 1.16 1.185 V
OVLOHYS OVLO hysteresis current OVLO = 1 V –28 –23 –18 µA
OVLODEL OVLO delay Delay to GATE high 19 µs
Delay to GATE low 9
OVLOBIAS OVLO bias current OVLO = 1 V 1 µA
POWER GOOD (PGD PIN)
PGDVOL Output low voltage ISINK = 2 mA 25 60 mV
PGDIOH Off leakage current VPGD = 17 V 1 µA
PGDDELAY Power Good delay VFB to VPG 115 ns
FB PIN
FBTH FB threshold VFB rising 1.141 1.167 1.19 V
FBHYS FB hysteresis current –31 –24 –18 µA
FBLEAK Off leakage current VFB = 1 V 1 µA
POWER LIMIT (PWR PIN)
PWRLIM Power limit sense voltage (VIN-SENSE) SENSE-OUT = 12 V, RPWR = 25 kΩ 9 12.5 15 mV
IPWR PWR pin current VPWR = 2.5 V –10 µA
RSAT(PWR) PWR pin impedance when disabled UVLO = 0.7 V 180 Ω
GATE CONTROL (GATE PIN)
IGATE Source current Normal operation –28 –22 –16 µA
Fault sink current UVLO = 1 V 1.5 2 2.5 mA
POR circuit breaker sink current VIN - SENSE = 150 mV or VIN < RPOR, VGATE = 5 V 105 190 275 mA
VGATE Gate output voltage in normal operation GATE voltage with respect to ground 17 18.8 20.3 V
OUT PIN
IOUT-EN OUT bias current, enabled OUT = VIN, normal operation 16 µA
IOUT-DIS OUT bias current, disabled(2) Disabled, OUT = 0 V, SENSE = VIN –12 µA
CURRENT LIMIT
VCL Threshold voltage CL = GND 22.5 25 27 mV
CL = GND, TJ = 10°C to 85°C 23 25 27
CL = VDD 42.3 46 49.7
ISENSE SENSE input current Enabled, SENSE = OUT 33 µA
Disabled, OUT = 0 V 46
Enabled, OUT = 0 V 45
CIRCUIT BREAKER
VCB Threshold voltage × 1.8 VIN - SENSE, CL = GND, CB = GND 35 45 55 mV
CB:CL ratio CB = GND 1.6 1.8 2
VCB Threshold voltage × 3.6 VIN - SENSE, CL = GND, CB = VDD 70 90 110 mV
CB:CL ratio CB = VDD 3.1 3.6 4
TIMER (TIMER PIN)
VTMRH Upper threshold 1.54 1.7 1.85 V
VTMRL Lower threshold Restart cycles 0.85 1 1.07 V
End of 8th cycle 0.3 V
Re-enable threshold 0.3 V
ITIMER Insertion time current TIMER pin = 2 V –3 –5.5 –8 µA
Sink current, end of insertion time 1.4 1.9 2.4 mA
Fault detection current –120 –90 –60 µA
Fault sink current 2.8 µA
DCFAULT Fault restart duty cycle 0.67%
INTERNAL REFERENCE
VREF Reference voltage 2.703 2.73 2.757 V
ADC AND MUX
Resolution 12 Bits
INL Integral non-linearity ADC only ±1 LSB
TELEMETRY ACCURACY
IINFSR Current input full scale range CL = GND 30.2 mV
CL = VDD 60.4 mV
IINLSB Current input LSB CL = GND 7.32 µV
CL = VDD 14.64 µV
VAUXFSR VAUX input full scale range 1.16 V
VAUXLSB VAUX input LSB 283.2 µV
VINFSR Input voltage full scale range 18.7 V
VINLSB Input voltage LSB 4.54 mV
IINACC Input current accuracy VIN – SENSE = 25 mV, CL = GND –1.2% 1%
VIN – SENSE = 25 mV, CL = GND
TJ = 10°C to 85°C
–1% 1%
VIN – SENSE = 50 mV, CL = VDD –1.8% 1.8%
VIN – SENSE = 50 mV, CL = GND
TJ = 10°C to 85°C
–5% 5%
VACC VAUX, VIN, VOUT accuracy VIN, VOUT = 12 V
VAUX = 1 V
–1% 1.2%
VIN, VOUT = 12 V
VAUX = 1 V
TJ = 10°C to 85°C
–1% 1%
PINACC Input power accuracy VIN = 12 V, VIN – SENSE = 25 mV,
CL = GND
–2.3% 2%
VIN = 12 V, VIN – SENSE = 25 mV,
CL = GND, TJ = 10°C to 85°C
–2% 2%
REMOTE DIODE TEMPERATURE SENSOR
TACC Temperature accuracy using local diode TA = 10°C to 85°C 2 10 °C
Remote diode resolution 9 bits
IDIODE External diode current source High level 250 300 µA
Low level 9.4 µA
Diode current ratio 26
PMBUS PIN THRESHOLDS (SMBA, SDA, SCL)
VIL Data, clock input low voltage 0.8 V
VIH Data, clock input high voltage 2.1 5.5 V
VOL Data output low voltage IPULLUP = 500 µA 0 0.4 V
ILEAK Input leakage current SDA, SMBA, SCL = 5 V 1 µA
CONFIGURATION PIN THRESHOLDS (CB, CL, RETRY)
VIH Threshold voltage 3 V
ILEAK Input leakage current CL, CB, RETRY = 5 V 1 mA
Current out of a pin is indicated as a negative value.
OUT bias current (disabled) due to leakage current through an internal 0.9 MΩ resistance from SENSE to VOUT.
All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Timing Requirements: SMBus Communications

MIN MAX UNIT
FSMB SMBus Operating Frequency 10 400 kHz
TBUF Bus free time between Stop and Start Condition 1.3 µs
THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. 0.6 µs
TSU:STA Repeated Start Condition setup time 0.6 µs
TSU:STO Stop Condition setup time 0.6 µs
THD:DAT Data hold time 300 ns
TSU:DAT Data setup time 100 ns
TTIMEOUT Clock low timeout(1) 25 35 ms
TLOW Clock low period 1.5 µs
THIGH Clock high period(2) 0.6 µs
TLOW:SEXT Cumulative clock low extend time (slave device)(3) 25 ms
TLOW:MEXT Cumulative low extend time (master device)(4) 10 ms
TF Clock or Data Fall Time(5) 20 300 ns
TR Clock or Data Rise Time(5) 20 300 ns
Devices participating in a transfer will timeout when any clock low exceeds the value of TTIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than TTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
THIGH MAX provides a simple method for devices to detect bus idle conditions.
TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop.
Rise and fall time is defined as follows: TR = ( VILMAX – 0.15) to (VIHMIN + 0.15) x TF = 0.9 VDD to (VILMAX – 0.15)

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
tCL Response time VIN-SENSE stepped from 0 mV to 80 mV 1.2 µs
CIRCUIT BREAKER
tCB Response time VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load TJ = –40°C to 85°C 0.6 1.2 µs
TIMER (TIMER PIN)
tFAULT_DELAY Fault to GATE low delay TIMER pin reaches the upper threshold 17 µs
ADC AND MUX
tAQUIRE Acquisition + Conversion Time Any channel 100 µs
tRR Acquisition Round Robin Time Cycle all channels 1 ms
LM25066A 301460a1.gif Figure 1. SMBus Timing Diagram

Typical Characteristics

Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
LM25066A 30115871.gif
Figure 2. VIN Pin Current
LM25066A 30115875.gif Figure 4. SENSE Pin Current (Disabled)
LM25066A 30115873.gif Figure 6. OUT Pin Current (Disabled)
LM25066A 30115877.gif Figure 8. GATE Pin Source Current
LM25066A 30115878.gif Figure 10. PGD Low Voltage
LM25066A 30115882.gif Figure 12. UVLO Hysteresis Current
LM25066A 30115883.gif Figure 14. OVLO Threshold
LM25066A 30115880.gif Figure 16. FB Pin Hysteresis
LM25066A 30115887.gif
Figure 18. Current Limit Threshold
LM25066A 30115890.gif Figure 20. Reference Voltage
LM25066A 30115892.gif Figure 22. Start-up (Short Circuit VOUT)
LM25066A 30115894.gif Figure 24. Start-up (UVLO, OVLO)
LM25066A 30115896.gif Figure 26. Current Limit Event (CL = GND)
LM25066A 30115898.gif Figure 28. Retry Event (Retry = GND)
LM25066A 301158a8.gif Figure 30. IIN Measurement Accuracy
(VIN – SENSE = 25 mV)
LM25066A 30115876.gif Figure 3. SENSE Pin Current (Enabled)
LM25066A 30115874.gif Figure 5. OUT Pin Current (Enabled)
LM25066A 30115872.gif Figure 7. GATE Pin Voltage
LM25066A 30115889.gif Figure 9. Power Limit Threshold
LM25066A 30115881.gif Figure 11. UVLO Threshold
LM25066A 30115879.gif Figure 13. FB Threshold
LM25066A 30115884.gif Figure 15. OVLO Hysteresis
LM25066A 30115886.gif
Figure 17. Current Limit Threshold
LM25066A 30115888.gif Figure 19. Circuit Breaker Threshold (CL = VDD)
LM25066A 30115891.gif
Figure 21. Start-up (Insertion Delay)
LM25066A 30115893.gif Figure 23. Start-up (5-A Load)
LM25066A 30115895.gif Figure 25. Start-up (PGOOD)
LM25066A 30115897.gif Figure 27. Circuit Breaker Event (CL = CB = GND)
LM25066A 30115899.gif Figure 29. Latch Off (Retry = VDD)
LM25066A 301158a9.gif Figure 31. PIN Measurement Accuracy
(VIN – SENSE = 25 mV)