SNVSAT9 June 2017 LM25145
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
To expedite the process of designing of a LM25145based regulator for a given application, please use the LM25145 Quickstart Calculator available as a free download, as well as numerous LM25145 reference designs populated in TI Designs™ reference design library, or the designs provided in Typical Applications. The LM25145 is also WEBENCH® Designer enabled.
Comprehensive knowledge and understanding of the power train components are key to successfully completing a synchronous buck regulator design.
For most applications, choose an inductance such that the inductor ripple current, ΔI_{L}, is between 30% and 40% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a peak inductor current given by Equation 8.
Check the inductor datasheet to ensure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced noload input current and higher lightload efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.
Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, C_{OUT}, filters the inductor ripple current and provides a reservoir of charge for stepload transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.
Based on the static specification of peaktopeak output voltage ripple denoted by ΔV_{OUT}, choose an output capacitance that is larger than that given by Equation 9.
Figure 42 conceptually illustrates the relevant current waveforms during both load stepup and stepdown transitions. As shown, the largesignal slew rate of the inductor current is limited as the inductor current ramps to match the new loadcurrent level following a load transient. This slewrate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load stepup transient. Similarly, during and after a load stepdown transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
In a typical regulator application of 24V input to low output voltage (for example, 5 V), it should be recognized that the loadoff transient represents worstcase. In that case, the steadystate duty cycle is approximately 10% and the largesignal inductor current slew rate when the duty cycle collapses to zero is approximately –V_{OUT}/L. Compared to a loadon transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a loadoff transient (denoted as ΔV_{OVERSHOOT} with step reduction in output current given by ΔI_{OUT}), the output capacitance should be larger than
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 47µF, 10V, X7R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the loadoff transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid and highfrequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides lowfrequency energy storage to cope with load transient demands.
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switchingfrequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the highside MOSFET and the source of the lowside MOSFET. The input capacitor RMS current is given by Equation 11.
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I_{OUT} − I_{IN}) during the D interval and sinks I_{IN} during the 1−D interval. Thus, the input capacitors conduct a squarewave current of peaktopeak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESRrelated ripple component, the peaktopeak ripple voltage amplitude is given by Equation 12.
The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_{IN}, is given by Equation 13.
LowESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with highQ ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2μF 100V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature.
The choice of power MOSFETs has significant impact on DCDC regulator performance. A MOSFET with low onstate resistance, R_{DS(on)}, reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_{DS(on)} of a MOSFET, the higher the gate charge and output charge (Q_{G} and Q_{OSS} respectively), and vice versa. As a result, the product R_{DS(on)} × Q_{G} is commonly specified as a MOSFET figureofmerit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in an LM25145 application are as follows:
The MOSFETrelated power losses are summarized by the equations presented in Table 2, where suffixes 1 and 2 represent highside and lowside MOSFET parameters, respectively. While the influence of inductor ripple current is considered, secondorder loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM25145 Quickstart Calculator to assist with power loss calculations.
POWER LOSS MODE  HIGHSIDE MOSFET  LOWSIDE MOSFET 

MOSFET Conduction^{(2)}^{(3)}  
MOSFET Switching  Negligible  
MOSFET Gate Drive^{(1)}  
MOSFET Output Charge^{(4)}  
Body Diode Conduction 
N/A  
Body Diode Reverse Recovery^{(5)} 
The highside (control) MOSFET carries the inductor current during the PWM ontime (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a highside MOSFET that balances conduction and switching loss contributions. The total power dissipation in the highside MOSFET is the sum of the losses due to conduction, switching (voltagecurrent overlap), output charge, and typically twothirds of the net loss attributed to body diode reverse recovery.
The lowside (synchronous) MOSFET carries the inductor current when the highside MOSFET is off (or 1–D interval). The lowside MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the transition deadtimes. The LM25145, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.
In high stepdown ratio applications, the lowside MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the lowside MOSFET for low R_{DS(on)}. In cases where the conduction loss is too high or the target R_{DS(on)} is lower than available in a single MOSFET, connect two lowside MOSFETs in parallel. The total power dissipation of the lowside MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically onethird of the net loss attributed to body diode reverse recovery. The LM25145 is well suited to drive TI's comprehensive portfolio of NexFET™ power MOSFETs.
The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue dashed rings in the schematic embedded in Table 3.
The compensation network typically employed with voltagemode control is a TypeIII circuit with three poles and two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining compensator pole located at onehalf switching frequency to attenuate high frequency noise. The resistor divider network to FB determines the desired output voltage. Note that the lower feedback resistor, R_{FB2}, has no impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias voltage and temperature.



POWER STAGE POLES  POWER STAGE ZEROS  COMPENSATOR POLES  COMPENSATOR ZEROS 
The smallsignal openloop response of a buck regulator is the product of modulator, power train and compensator transfer functions. The power stage transfer function can be represented as a complex pole pair associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low frequency) gain of the modulator and power stage is V_{IN}/V_{RAMP}. The gain from COMP to the average voltage at the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM25145 (15 V/V or 23.5 dB).
Complete expressions for smallsignal frequency analysis are presented in Table 4. The transfer functions are denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by its loop gain but by its performance related characteristics, namely closedloop output impedance and audio susceptibility.
TRANSFER FUNCTION  EXPRESSION 

Openloop transfer function  
Dutycycletooutput transfer function  
Compensator transfer function^{(1)}  
Modulator transfer function 
An illustration of the openloop response gain and phase is given in Figure 43. The poles and zeros of the system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB) scale, the openloop gain is effectively the sum of the individual gain components from the modulator, power stage, and compensator (see Figure 44). The openloop response of the system is measured experimentally by breaking the loop, injecting a variablefrequency oscillator signal and recording the ensuing frequency response using a network analyzer setup.
If the pole located at ω_{p1} cancels the zero located at ω_{ESR} and the pole at ω_{p2} is located well above crossover, the expression for the loop gain, T_{v}(s) in Table 4, can be manipulated to yield the simplified expression given in Equation 14.
Essentially, a multiorder system is reduced to a singleorder approximation by judicious choice of compensator components. A simple solution for the crossover frequency, denoted as f_{c} in Figure 43, with TypeIII voltagemode compensation is derived as shown in Equation 15 and Equation 16.
The loop crossover frequency is usually selected between onetenth to onefifth of switching frequency. Inserting an appropriate crossover frequency into Equation 15 gives a target for the midband gain of the compensator, K_{mid}. Given an initial value for R_{FB1}, R_{FB2} is then selected based on the desired output voltage. Values for R_{C1}, R_{C2}, C_{C1}, C_{C2} and C_{C3} are calculated from the design expressions listed in Table 5, with the premise that the compensator poles and zeros are set as follows: ω_{z1} = 0.5·ω_{o}, ω_{z2} = ω_{o}, ω_{p1} = ω_{ESR}, ω_{p2} = ω_{SW}/2.
RESISTORS  CAPACITORS 

Referring to the bode plot in Figure 43, the phase margin, indicated as φ_{M}, is the difference between the loop phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why C_{C1} is scaled by a factor of 2 above). This helps mitigate the phase dip associated with the LC filter, particularly at light loads when the Qfactor is higher and the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an underdamped transient response in the time domain.
The power supply designer now has all the necessary expressions to optimally position the loop crossover frequency while maintaining adequate phase margin over the required line, load and temperature operating ranges. The LM25145 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot as needed.
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance.
The EMI filter design steps are as follows:
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it by the input impedance (the impedance is defined by the existing input capacitor C_{IN}), a formula is derived to obtain the required attenuation as shown by Equation 18.
V_{MAX} is the allowed dBμV noise level for the applicable EMI standard, for example EN55022 Class B. C_{IN} is the existing input capacitance of the buck regulator, D_{MAX} is the maximum duty cycle, and I_{PEAK} is the peak inductor current. For filter design purposes, the current at the input can be modeled as a squarewave. Determine the EMI filter capacitance C_{F} from Equation 19.
Adding an input filter to a switching regulator modifies the controltooutput transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 20.
The purpose of R_{D} is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C_{D} blocks the DC component of the input voltage to avoid excessive power dissipation in R_{D}. Capacitor C_{D} should have lower impedance than R_{D} at the resonant frequency with a capacitance value greater than that of the input capacitor C_{IN}. This prevents C_{IN} from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by L_{IN} and C_{IN} is too high). An electrolytic capacitor C_{D} can be used for damping with a value given by Equation 21.
Select the damping resistor R_{D} using Equation 22.

For stepbystep design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of an LM25145powered implementation, please refer to TI Designs reference design library. 
Figure 46 shows the schematic diagram of a 5V, 20A buck regulator with a switching frequency of 500 kHz. In this example, the target fullload efficiency is 94% at a nominal input voltage of 24 V that ranges from 6.5 V to as high as 32 V. The switching frequency is set by means of a synchronization input signal at 500 kHz, and the freerunning switching frequency (in the event that the synchronization signal is removed) is set at 450 kHz by resistor R_{RT}. In terms of control loop performance, the target loop crossover frequency is 70 kHz with a phase margin greater than 50°. The output voltage softstart time is 4 ms.
NOTE
This and subsequent design examples are provided herein to showcase the LM25145 controller in several different applications. Depending on the source impedance of the input supply bus, an electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage and high output current operating conditions. See Power Supply Recommendations for more detail.
The intended input, output, and performancerelated parameters pertinent to this design example are shown in Table 6.
DESIGN PARAMETER  VALUE 

Input voltage range (steadystate)  6.5 V to 32 V 
Input transient voltage (peak)  42 V 
Output voltage and current  5 V, 20 A 
Input voltage UVLO thresholds  6.5 V on, 6 V off 
Switching frequency (SYNC in)  500 kHz 
Output voltage regulation  ±1% 
Load transient peak voltage deviation  < 100 mV 
The design procedure for an LM25145based regulator for a given application is streamlined by using the LM25145 Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power Designer.
The selected buck converter powertrain components are cited in Table 7, and many of the components are available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in Power MOSFETs.
The current limit setpoint in this design is set at 26 A based on the resistor R_{ILIM} and the 2mΩ R_{DS(on)} of the lowside MOSFET (typical at T_{J} = 25°C and V_{GS} = 7.5 V). This design uses a lowDCR, metalpowder inductor and an allceramic output capacitor implementation.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  7  10 µF, 50 V, X7R, 1210, ceramic  TDK  C3225X7R1H106M 
Murata  GRM32ER71H106KA12L  
AVX  12105C106KAT2A  
Kemet  C1210C106K5RACTU  
Taiyo Yuden  UMK325AB7106MMT  
C_{OUT}  7  47 µF, 10 V, X7R, 1210, ceramic  Murata  GRM32ER71A476KE15L 
Taiyo Yuden  LMK325B7476MMTR  
AVX  1210ZC476KAT2A  
Kemet  C1210C476M8RAC7800  
L_{F}  1  1 µH, 2.3 mΩ, 40 A, 11.15 × 10 × 3.8 mm  Cyntec  CMLE104T1R0MS2R307 
1.2 µH, 1.8 mΩ, 25 A, 10.2 × 10.2 × 4.7 mm  Würth Electronik  WE HCI 744325120  
1 µH, 2.3 mΩ, 38 A, 10.9 × 10 × 5.0 mm  Panasonic  ETQP5M1R0YLC  
1 µH, 2.2 mΩ, 36 A, 10.5 × 10 × 6.5 mm  TDK  SPM10065VTD  
Q_{1}  1  40 V, 3.7 mΩ, highside MOSFET, SON 5 × 6  Texas Instruments  CSD18503Q5A 
Q_{2}  1  40 V, 2 mΩ, lowside MOSFET, SON 5 × 6  Texas Instruments  CSD18511Q5A 
U_{1}  1  Wide V_{IN} synchronous buck controller  Texas Instruments  LM25145RGYR 
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SYNCIN tied to VCC 
V_{IN} step to 24 V  0.25Ω Load 
V_{IN} = 24 V  0.25Ω Load 
V_{IN} = 24 V 
V_{IN} = 24 V  I_{OUT} = 0 A 
SYNCIN tied to GND 
V_{IN} 24 V to 6 V  0.25Ω Load 
V_{IN} = 24 V  0.25Ω Load 
V_{IN} = 24 V 
V_{IN} = 24 V  I_{OUT} = 20 A 
Figure 57 shows the schematic diagram of a 425kHz, 12V output, 8A synchronous buck regulator intended for RF power applications.
An auxiliary 10V, 800mA rail to power noisesensitive circuits is available using the LP38798 ultralow noise LDO as a postregulator. The internal pullup of the EN pin of the LP38798 facilitates direct connection to the PGOOD of the LM25145 for sequential startup control.
The required input, output, and performance parameters for this application example are shown in Table 8.
DESIGN PARAMETER  VALUE 

Input voltage range (steadystate)  14.4 V to 36 V 
Input transient voltage (peak)  42 V 
Output voltage and current  12 V, 8 A 
Input UVLO thresholds  14 V on, 13.2 V off 
Switching frequency  425 kHz 
Output voltage regulation  ±1% 
Load transient peak voltage deviation, 4A load step, 1 A/µs  < 150 mV 
A high power density, highefficiency regulator solution is realized by using TI NexFET™ Power MOSFETs, such as CSD18543Q3A (60V, 8.5mΩ MOSFET in a SON 3.3mm × 3.3mm package), together with a lowDCR inductor and allceramic capacitor design. The design occupies 15 mm × 15 mm on a singlesided PCB. The overcurrent (OC) setpoint in this design is set at 11 A based on the resistor R_{ILIM} and the 8.5mΩ R_{DS(on)} of the lowside MOSFET (typical at T_{J} = 25°C and V_{GS} = 7.5 V). Connecting VCC to either V_{OUT1} or V_{OUT2} using a series diode reduces bias power dissipation and improves efficiency, especially at light loads.
The selected buck converter powertrain components are cited in Table 9, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Using the LM25145 Quickstart Calculator, compensation components are selected based on a target loop crossover frequency of 70 kHz and phase margin greater than 55°. The output voltage softstart time is 4 ms based on the selected softstart capacitance, C_{SS}, of 47 nF.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  4  10 µF, 50 V, X7R, 1210, ceramic  TDK  C3225X7R1H106M 
Murata  GRM32ER71H106KA12L  
AVX  12105C106KAT2A  
C_{OUT}  4  22 µF, 25 V, X7R, 1210, ceramic  Murata  GRM32ER71E226KE15L 
Taiyo Yuden  TMK325B7226MMTR  
TDK  C3225X7R1E226M  
L_{F}  1  5.6 µH, 17 mΩ, 18 A, 10.85 × 10 × 3.8 mm  Cyntec  CMLS104T5R6MS 
5.6 µH, 20 mΩ, 14 A, 10.85 × 10 × 3.8 mm  Delta  MPT10405R6H1  
5.6 µH, 16 mΩ, 12 A, 10.7 × 10 × 4 mm  Bourns  SRP10405R6M  
5.6 µH, 19.3 mΩ, 16 A, 11 × 10 × 4 mm  Laird  MGV10045R6M10  
6.8 µH, 17.5 mΩ, 14 A, 11 × 10 × 3.8 mm  Würth Electronik  WELHMI 74437368068  
6.8 µH, 17.9 mΩ, 25 A, 10.5 × 10 × 4 mm  TDK  SPM10040VT6R8MD  
6.8 µH, 18.3 mΩ, 12.1 A, 10.7 × 10 × 4 mm  Panasonic  ETQP4M6R8KVC  
Q_{1}, Q_{2}  2  60 V, 8 mΩ, MOSFET, SON 3 × 3  Texas Instruments  CSD18543Q3A 
U_{1}  1  Wide V_{IN} synchronous buck controller  Texas Instruments  LM25145RGYR 
U_{2}  1  Ultralow noise and highPSRR LDO for RF and analog circuits, 4mm × 4mm 12pin WSON  Texas Instruments  LP38798SDADJ 
If needed, a 2.2Ω resistor can be added in series with C_{BST} is used to slow the turnon transition of the highside MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dtinduced shootthrough of the lowside MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the lowside MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.
V_{IN} step to 24 V  1.5Ω Load 
V_{IN} = 24 V  1.5Ω Load 
V_{IN} = 24 V  I_{OUT} = 0 A 
V_{IN} = 24 V 
I_{OUT} = 8 A 
V_{IN} = 24 V  I_{OUT} = 4 A 
1.5Ω Load 
V_{IN} = 24 V  1.5Ω Load 
V_{IN} = 24 V  I_{OUT} = 0 A 
V_{IN} = 24 V 
I_{OUT} = 8 A 

For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power House blog series. 
Figure 70 shows the schematic diagram of a 10A synchronous buck regulator for a DSP core voltage supply.
For this application example, the intended input, output, and performance parameters are listed in Table 10.
DESIGN PARAMETER  VALUE 

Input voltage range (steadystate)  6 V to 36 V 
Input transient voltage (peak)  42 V 
Output voltage and current  0.9 V to 1.1 V, 10 A 
Output voltage regulation  ±1% 
Load transient peak voltage deviation, 10A step  < 120 mV 
Switching frequency  300 kHz 
The schematic diagram of a 300kHz, 24V nominal input, 10A regulator powering a KeyStone™ DSP is given in Figure 70. This high stepdown ratio design leverages the low 40ns minimum controllable ontime of the LM25145 controller to achieve stable, efficient operation at very low duty cycles. 60V power MOSFETs, such as TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a lowDCR, metalpowder inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 32.
The important components for this design are listed in Table 11.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  3  10 µF, 50 V, X7R, 1210, ceramic  TDK  C3225X7R1H106M 
Murata  GRM32ER71H106KA12L  
AVX  12105C106KAT2A  
C_{OUT}  4  100 µF, 6.3V, X7S, 1210, ceramic  Murata  GRM32EC70J107ME15L 
Taiyo Yuden  JMK325AC7107MMP  
100 µF, 6.3V, X5R, 1206, ceramic  Murata  GRM31CR60J107ME39K  
TDK  C3216X5R0J107M  
Würth Electronik  885012108005  
L_{F}  1  1 µH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mm  Cyntec  CMLE063T1R0MS 
1 µH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mm  Würth Electronik  WE XHMI 74439344010  
1 µH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mm  Panasonic  ETQP3M1R0YFN  
1 µH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mm  Coilcraft  XEL6030102ME  
Q_{1}  1  60 V, 8.5 mΩ, highside MOSFET, SON 3 × 3  Texas Instruments  CSD18543Q3A 
Q_{2}  1  60 V, 4 mΩ, lowside MOSFET, SON 5 × 6  Texas Instruments  CSD18531Q5A 
U_{1}  1  Wide V_{IN} synchronous buck controller  Texas Instruments  LM25145RGYR 
U_{2}  1  6 or 4bit VID voltage programmer, WSON10  Texas Instruments  LM10011SD 
U_{3}  1  KeyStone™ DSP  Texas Instruments  TMS320C667x 
The regulator output current requirements are dependent upon the baseline and activity power consumption of the DSP in a realuse case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM25145 FB pin to allow continuous optimization of the core voltage. The SmartReflexenabled DSP provides 6bit information using the VCNTL opendrain I/Os to command the output voltage setpoint with 6.4mV step resolution.^{(1)}
V_{OUT} = 1.1 V  V_{AUX} = 8 V 
V_{IN} = 24 V  0.11Ω Load 
V_{IN} step to 24 V  0.11Ω Load 
V_{IN} = 24 V 