SNVS896B August 2013 – November 2014 LM27403
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
To expedite the process of designing of a LM27403based regulator for a given application, please use the LM27403 Quickstart Design Tool available as a free download. As well as numerous LM27403 reference designs populated in TI Designs™ reference design library, five designs are provided in the Typical Applications section of this datasheet. The LM27403 is also WEBENCH® Designer enabled.
Comprehensive knowledge and understanding of the power train components are key to successfully completing a buck regulator design. The LM27403 Design Tool and WEBENCH are available to assist the designer with selection of these components for a given application.
For most applications, choose an inductance such that the inductor ripple current, ΔI_{L}, is between 20% and 40% of the maximum dc output current. Choose the inductance using Equation 10:
Check the inductor datasheet to ensure that the inductor's saturation current is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced noload input current and higher lightload efficiency. However, ferrite core materials exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that an inductor's saturation current generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.
Ordinarily, the regulator’s output capacitor energy store combined with the control loop response are prescribed to maintain the integrity of the output voltage within both the static and dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics – equivalent series resistance (ESR) and equivalent series inductance (ESL) – take increasing precedence in shaping the regulator’s load transient response as the output current ramp amplitude and slew rate increase.
So, the output capacitor, C_{OUT}, exists to filter the inductor ripple current and provide a reservoir of charge for step load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.
Based on the static specification of peaktopeak output voltage ripple denoted by ΔV_{O}, choose an output capacitance that is larger than
Figure 38 conceptually illustrates the relevant current waveforms during both load stepup and stepdown transitions. As shown, the largesignal slew rate of the inductor current is limited as the inductor current ramps to match the new loadcurrent level following a load transient. This slewrate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the loadon transient. Similarly, during and after a loadoff transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that needs to be depleted as quickly as possible.
In a typical regulator application of 12V input to low output voltage (say 1.2 V), it should be recognized that the loadoff transient represents worstcase. In that case, the steadystate duty cycle is approximately 10% and the largesignal inductor current slew rate when the duty cycle collapses to zero is approximately –V_{OUT}/L. Compared to a loadon transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and rein in the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a loadoff transient (denoted as ΔV_{overshoot} with step reduction in output current given by ΔI_{o}), the output capacitance should be larger than
The ESR of a capacitor is provided in the manufacturer’s datasheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some ESR and ESL as well. Ceramic output capacitors, on the other hand, are such that the impedances related to the ESR and ESL are small at the switching frequency, and the capacitive impedance dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied voltage and operating temperature.
Ignoring the ESR term in Equation 11 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 100µF, 6.3V, X5R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 12 to quantify if additional capacitance is necessary to meet the loadoff transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale of paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range of interest. While the ceramic provides excellent mid and highfrequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides lowfrequency energy storage to cope with loadtransient demands.
Input capacitors are necessary to limit the input ripple voltage while switchingfrequency ac current to the buck power stage. It is generally recommended to use X5R or X7R dielectric ceramic capacitors, thus providing low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the highside MOSFET and the source of the lowside MOSFET.
The input capacitors' RMS current is given by Equation 13.
The highest requirement for input capacitor RMS current rating occurs at D = 0.5, at which point the RMS current rating should be greater than half the output current.
Ideally, the dc component of input current is provided by the input voltage source and the ac component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude I_{o}−I_{IN} during the D interval and sinks I_{IN} during the 1−D interval. Thus, the input capacitors conduct a squarewave current of peaktopeak amplitude equal to the output current. It follows that the resultant capacitive component of ac ripple voltage is a triangular waveform. Together with the ESRrelated ripple component, the peaktopeak ripple voltage amplitude is given by Equation 14.
The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_{IN}, is given by Equation 15.
Low ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with highQ ceramics. One bulk capacitor of sufficiently high current rating and one or two 10μF 25V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature.
The choice of MOSFET has significant impact on DCDC regulator performance. A MOSFET with low onstate resistance, R_{DS(on)}, reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_{DS(on)} of a MOSFET, the higher the gate charge, Q_{G}, and vice versa. As a result, the product R_{DS(on)}*Q_{G} is commonly specified as a MOSFET figureofmerit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting MOSFET selection in an LM27403 application are as follows:
The MOSFETrelated power losses are summarized by the equations presented in Table 2. While the influence of inductor ripple current is considered, secondorder loss modes, such as those related to parasitic inductances, are not discussed. Consult the LM27403 Quickstart Design Tool to assist with power loss calculations.
Power Loss Mode  HighSide MOSFET  LowSide MOSFET 

Conduction ^{(2)}  ^{(3)}  
Switching  Negligible  
Gate Drive^{(1)}  
Body Diode Conduction  N/A  
Body Diode Reverse Recovery 
The highside (control) MOSFET carries the inductor current during the PWM on time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a highside MOSFET that balances conduction and switching loss contributions. The total power dissipation in the highside MOSFET is the sum of the losses due to conduction, switching and typically twothirds of the net loss attributed to body diode reverse recovery.
The lowside (synchronous) MOSFET carries the inductor current when the highside MOSFET is off (or 1–D interval). The lowside MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the deadtime. The LM27403, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.
In high input voltage and low output voltage applications, the lowside MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the lowside MOSFET for low R_{DS(on)}. In cases where the conduction loss is too high or the target R_{DS(on)} is lower than available in a single MOSFET, connect two lowside MOSFETs in parallel. The total power dissipation of the lowside MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically onethird of the net loss attributed to body diode reverse recovery.
The LM27403 is well matched to TI's comprehensive portfolio of 25V and 30V NexFET™ family of power MOSFETs. In fact, the LM27403 is ideally suited to driving the Power Block NexFET™ modules with integrated highside and lowside MOSFETs. Excellent efficiency is obtained by virtue of reduced parasitics and exemplary thermal performance of the Power Block MOSFET implementation. See the Typical Applications section for more details.
The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue dashed rings in the schematic embedded in Table 3.
The compensation network typically employed with voltagemode control is a typeIII circuit with three poles and two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation strategy then is to use two compensator zeros to counteract the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining compensator pole located at onehalf switching frequency to attenuate high frequency noise. Finally, a resistor divider network to FB determines the desired output voltage. Note that the lower feedback resistor, R_{FB2}, has no impact on the control loop from an ac standpoint since the FB node is the input to an error amplifier and is effectively at ac ground. Hence, the control loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias voltage and temperature.



Power Stage Poles  Power Stage Zeros  Compensator Poles  Compensator Zeros 
^{(1)}  
^{(2)} 
The smallsignal openloop response of a buck regulator is the product of modulator, power train and compensator transfer functions. The power stage transfer function can be represented as a complex pole pair associated with the output LC filter and a zero related to the output capacitor's ESR. The dc (and low frequency) gain of the modulator and power stage is V_{IN}/V_{RAMP}. Representing the gain from COMP to the average voltage at the input of the LC filter, this is held essentially constant by the LM27403's PWM line feedforward feature at 9 V/V or 19 dB.
Complete expressions for smallsignal frequency analysis are presented in Table 4. The transfer functions are denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by its loop gain but by its performance related characteristics, namely closedloop output impedance and audio susceptibility.
PARAMETER  EXPRESSION 

Openloop transfer function  
Dutycycletooutput transfer function  
Compensator transfer function^{(1)}  
Modulator transfer function 
An illustration of the openloop response gain and phase is given in Figure 39. The poles and zeros of the system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB) scale, the openloop gain is effectively the sum of the individual gain components from the modulator, power stage and compensator – this is clear from Figure 40. The openloop response of the system is measured experimentally by breaking the loop, injecting a variablefrequency oscillator signal and recording the ensuing frequency response using a network analyzer setup.
If the pole located at ω_{p1} cancels the zero located at ω_{ESR} and the pole at ω_{p2} is located well above crossover, the expression for the loop gain, T_{v}(s) in Table 4, can be manipulated to yield the simplified expression given in Equation 16.
Essentially, a multiorder system is reduced to a single order approximation by judicious choice of compensator components. A simple solution for the crossover frequency, denoted as f_{c} in Figure 39, with typeIII voltagemode control is derived as in Equation 17.
The loop crossover frequency is usually selected between onetenth to onefifth of switching frequency. Inserting an appropriate crossover frequency into Equation 17 gives a target for the compensator's midband gain, K_{mid}. Given an initial value for R_{FB1}, R_{FB2} is then selected based on the desired output voltage. Values for R_{C1}, R_{C2}, C_{C1}, C_{C2} and C_{C3} are calculated from the designoriented expressions listed in Table 5, with the premise that the compensator poles and zeros are set as follows: ω_{z1} = 0.5ω_{o}, ω_{z2} = ω_{o}, ω_{p1} = ω_{ESR}, ω_{p2} = ω_{sw}/2.
RESISTORS  CAPACITORS 

Referring to the bode plot in Figure 39, the phase margin, indicated as φ_{M}, is the difference between the loop phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why C_{C1} is scaled by a factor of 2 above). This helps to mitigate the phase dip associated with the LC filter, particularly at light loads when the Qfactor is higher and the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an underdamped transient response in the time domain.
The power supply designer now has all the tools at his/her disposal to optimally position the loop crossover frequency while maintaining adequate phase margin over the power supply's required line, load and temperature operating ranges.
The schematic diagram of a 25A regulator is given in Figure 41. In this example, the target fullload efficiencies are 91% and 97% at 1.2V and 5.3V output voltages, respectively, based on a nominal input voltage of 12 V that ranges from 6.5 V to 20 V. Output voltage is adjusted simply by changing R_{FB2}. The switching frequency is set by means of a synchronization signal at 300 kHz, and freerunning switching frequency (in the event that the synchronization signal is removed) is set to 250 kHz by resistor R_{FADJ}. In terms of control loop performance, the target loop crossover frequency is 45 kHz with a phase margin in excess of 50°. The output voltage softstart time is 8 ms.
The design procedure for an LM27403based converter for a given application is streamlined by using the LM27403 QuickStart Design Tool available as a free download, or by availing of TI's WEBENCH® Designer online software. Such tools are complemented by the availability of two LM27403 evaluation module (EVM) designs as well as numerous LM27403 reference designs populated in TI Designs™ reference design library.
The current limit setpoint in this design is set at 28.5 A, based on resistor R_{ISET} and the inductor DCR (1.1 mΩ typ at 25°C). Of course, the current limit setpoint should always be selected such that the operating current level does not exceed the saturation current specification of the chosen inductor. The component values for the DCR sense network (R_{S} and C_{S} in Figure 41) are chosen based on making the R_{S}C_{S} product approximately equal to L/R_{dcr}, as recommended in the Current Sensing: CS+ and CS– section.
The selected buck converter powertrain components are cited in Table 6, and many of the components are available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in the Power MOSFETs section.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  3  22 µF, 25 V, X7R, 1210 ceramic  Kemet  C1210C226M3RACTU 
Taiyo Yuden  TMK325B7226MMTR  
Murata  GRM32ER71E226KE15L  
C_{OUT}  4  47 µF, 10 V, X7R, 1210 ceramic  Taiyo Yuden  LMK325B7476MMTR 
Murata  GRM32ER71A476KE15L  
C_{BULK}  1  330 µF, 6.3 V, 9 mΩ, D3L POSCAP  Sanyo  6TPF330M9L 
L_{1}  1  1.0 µH, 30 A, 1.1 mΩ ±10%, ferrite  Delta  HMP13601R063 
Q_{1}  1  25 V, highside MOSFET  Infineon  BSC032NE2LS 
Texas Instruments  CSD16322Q5  
Q_{2}  1  25 V, lowside MOSFET  Infineon  BSC010NE2LS 
Texas Instruments  CSD16415Q5 
The schematic diagram of a 600kHz, 30A regulator is given in Figure 46. The powertrain components are listed in Table 7.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER  

C_{IN}  3  10 µF, 25 V, X5R, 0805 ceramic  Taiyo Yuden  TMK212BBJ106KGT  
Murata  GRM21BR61E106KA73L  
TDK  C2012X5R1E106M  
C_{OUT}  1  100 µF, 6.3 V, X5R, 1206 ceramic  Taiyo Yuden  JMK316BJ107MLT  
Murarta  GRM31CR60J107ME39L  
TDK  C3216X5R0J107M  
Kemet  C1206C107M9PACTU  
L_{1}  1  300 nH, ferrite  35 A, 0.29 mΩ ±8%  Coiltronics  FP1107R1R30R 
34 A, 0.29 mΩ ±7%  Cyntec  PCDC1107R30EMO  
270 nH, ferrite  37 A, 0.24 mΩ ±5%  Coilcraft  SLC1175271MEC  
250 nH, ferrite  44 A, 0.37 mΩ ±7%  Wurth  744308025  
Q_{1}  1  30 V Power Block Q5D MOSFET Module, 5 mm x 6 mm  Texas Instruments  CSD87350Q5D 
A high power density, high efficiency solution is feasible by using TI NexFET™ Power Block module CSD87350Q5D (dual asymmetric MOSFETs in a SON 5mm x 6mm package) together with and lowDCR ferrite inductor and allceramic capacitor design. The design occupies 20 mm x 15 mm on a singlesided PCB. Knowing the cumulative resistance of the inductor DCR and Power Block MOSFET SW clip (approximately 1 mΩ at 25°C), resistor R_{ISET} positions the current limit setpoint at 28A. The output voltage is adjusted by choosing the resistance of R_{FB2} appropriately. Resistors R_{TRK1} and R_{TRK2} connected to the SS/TRACK pin define a coincidental tracking startup sequence from a master power supply, V_{TRACK}.
Additional input and/or output capacitance can be added if needed, but adjust the compensation if C_{OUT} changes. The T_{GR} pin of the Power Block MOSFET serves as a kelvin connection to the source of the highside MOSFET and represents the return path for the highside gate drive. Along with bootstrap capacitor, C_{BOOT}, T_{GR} is connected to the LM27403's SW pin.
The schematic diagram of a 450kHz, 12V nominal input, 15A regulator powering a KeyStone™ DSP is given in Figure 48. The important components are listed in Table 8. The regulator output current requirements are dependent upon the baseline and activity power consumptions of the DSP in a realuse case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM27403 FB pin to allow continuous optimization of the core voltage. The SmartReflexenabled DSP provides 6bit information using the VCNTL opendrain IOs^{(1)} to command the output voltage setpoint with 6.4mV step resolution. This design uses a TI NexFET™ Power Block module CSD87330Q3D (dual asymmetric MOSFETs in SON 3.3mm x 3.3mm package) together with lowDCR, metalpowder inductor and composite ceramic–polymer electrolytic output capacitor implementation.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  1  22 µF, 25 V, X5R, 1210 ceramic  Taiyo Yuden  TMK325BJ226MMT 
C_{BYPASS}  5  10 µF, 4 V, X5R, 0402 ceramic  Taiyo Yuden  AMK105BJ106MVF 
C_{BULK}  1  270 µF, 2 V, 6 mΩ, 3.2 Arms, 3.5 mm x 2.8 mm, POSCAP  Panasonic  2TPSF270M6E 
L_{1}  1  0.42 µH, 22 A, 1.55 mΩ ±7%, molded, 6.9 mm x 6.6 mm  Cyntec  PIME064TR42MS1R557 
Q_{1}  1  30 V Power Block Q3D MOSFET Module, 3.3 mm x 3.3 mm  Texas Instruments  CSD87330Q3D 
Q_{T}  1  2N3904 type NPN transistor, 40 V, 0.2 A, SOT523  Diodes, Inc.  MMBT3904T 
U_{2}  1  6 or 4bit VID Programmable Current DAC, WSON10  Texas Instruments  LM10011SD 
U_{3}  1  KeyStone™ DSP  Texas Instruments  TMS320C667x 
The schematic diagram of a 280kHz, 12V output, 10A buck regulator for RF power applications is given in Figure 49^{(1)}. A 10Ω resistor in series with C_{BOOT} is used to slow the turnon transition of the highside MOSFET, reducing the spike amplitude and ringing of the SW node waveform and minimizing the possibility of Cdv/dtinduced shootthrough of the lowside MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 1 nF) close to the SW node and GND^{(2)}. An auxiliary 10V, 800mA rail to power noisesensitive circuits is available using the LP38798 ultralow noise LDO as a postregulator. The internal pullup of the LP38798's EN pin facilitates direct connection to the LM27403's PGOOD for sequential startup control.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER 

C_{IN}  3  22 µF, 25 V, X5R, 1210 ceramic  Taiyo Yuden  TMK325BJ226MMT 
C_{BYP}  1  22 µF, 16 V, X7R, 1210 ceramic  Taiyo Yuden  EMK325B7226MMT 
C_{BULK}  1  180 µF, 16 V, 22 mΩ, 3.3 Arms, C6, OSCON  Panasonic  16SVPF180M 
L_{1}  1  4.7 µH, 15 A, 7 mΩ, flat wire high current  Wurth  7443551470 
Q_{1}  1  30 V, highside MOSFET  Texas Instruments  CSD17309Q3 
Q_{2}  1  30 V, lowside MOSFET  Infineon  BSC011NE3LS 
U_{2}  1  UltraLow Noise, High PSRR LDO for RF/Analog Circuits, 4mm x 4mm WSON12  Texas Instruments  LP38798SDADJ 
The schematic diagram of a 250kHz, 25A regulator is given in Figure 50. A high power density, ultrahigh efficiency solution is possible using two paralleled TI CSD87353Q5D NexFET™ Power Block modules (dual MOSFETs in a SON 5mm x 6mm package) and lowDCR ferrite inductor. The design occupies 25 mm x 15 mm on a twosided PCB. Knowing the cumulative resistance of the inductor DCR and Power Block MOSFET SW clip (approximately 0.8 mΩ at 25°C), resistor R_{ISET} positions the current limit setpoint at 30A. VDD is tied to VIN to maximize the gate drive voltage for the MOSFETs. Capacitor C_{DLY} defines a 3ms startup delay based on the current sourced from the UVLO/EN pin.
The powertrain components are listed in Table 10, and the filter components are available from multiple vendors. The T_{GR} pin of the Power Block MOSFET serves as a kelvin connection to the source of the highside MOSFET and represents the return path for the highside gate drive. Along with bootstrap capacitor, C_{BOOT}, T_{GR} is connected to the LM27403's SW pin.
REFERENCE DESIGNATOR  QTY  SPECIFICATION  MANUFACTURER  PART NUMBER  

C_{IN}  3  100 µF, 6.3 V, X5R, 1210 ceramic  Kemet  C1210C107M9PACTU  
TDK  C3225X5R0J107M  
Murata  GRM32ER60J107ME20K  
C_{OUT}  4  100 µF, 6.3 V, X5R, 1206 ceramic  Taiyo Yuden  JMK316BJ107MLT  
Murarta  GRM31CR60J107ME39L  
TDK  C3216X5R0J107M  
Kemet  C1206C107M9PACTU  
L_{1}  1  300 nH, ferrite  35 A, 0.29 mΩ ±8%  Coiltronics  FP1107R1R30R 
330 nH, ferrite  46 A, 0.32 mΩ ±7%  Wurth Electronik  744301033  
Q_{1}  2  30 V Power Block Q5D MOSFET Module, 5 mm x 6 mm  Texas Instruments  CSD87353Q5D 