The LM46000-Q1 only requires a few external components to convert from a wide range of supply voltage to output voltage. Figure 44 shows a basic schematic when BIAS is connected to V_{OUT} . This is recommended for V_{OUT} ≥ 3.3 V. For V_{OUT} < 3.3 V, BIAS must be connected to ground, as shown in Figure 45.
The LM46000-Q1 also integrates a full list of optional features to aid system design requirements, such as precision enable, V_{CC} UVLO, programmable soft start, output voltage tracking, programmable switching frequency, clock synchronization and power-good indication. Each application can select the features for a more comprehensive design. A schematic with all features utilized is shown in Figure 46.
The external components have to fulfill the needs of the application, but also the stability criteria of the device's control loop. The LM46000-Q1 is optimized to work within a range of external components. The LC output filter's inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM46000-Q1 device with the WEBENCH® Power Designer.
- Start by entering the input voltage (V_{IN}), output voltage (V_{OUT}), and output current (I_{OUT}) requirements.
- Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
- Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.
In most cases, these actions are available:
- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LM46000-Q1 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor R_{FBT} and bottom feedback resistor R_{FBB}. Equation 11 is used to determine the output voltage of the converter:
Equation 11.
Choose the value of the R_{FBT} to be 1 MΩ to minimize quiescent current to improve light load efficiency in this application. With the desired output voltage set to be 3.3 V and the V_{FB} = 1.016 V, the R_{FBB} value can then be calculated using Equation 11. The formula yields a value of 444.83 kΩ. Choose the closest available value of 442 kΩ for the R_{FBB}. See Adjustable Output Voltage for more details.
8.2.2.3 Switching Frequency
The default switching frequency of the LM46000-Q1 device is set at 500 kHz when RT pin is open circuit. The switching frequency is selected to be 500 kHz in this application for one less passive components. If other frequency is desired, use Equation 12 to calculate the required value for R_{T}.
Equation 12. R_{T}(kΩ) = 40200 / Freq (kHz) – 0.6
For 500 kHz, the calculated R_{T} is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching frequency at 500 kHz.
8.2.2.4 Input Capacitors
The LM46000-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 µF to 10 µF. A high-quality ceramic type X5R or X7R with sufficient voltage rating is recommended. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitor, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance may be required, especially if the LM46000-Q1 circuit is not located within approximately 5 cm from the input voltage source. The bulk input capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable or trace. The value for this capacitor is not critical but must be rated to handle the maximum input voltage including ripple.
For this design, a 10-µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance.
8.2.2.5 Inductor Selection
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is based on the desired peak-to-peak ripple current, Δi_{L}, that flows in the inductor along with the DC load current. As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to 40% of the 0.5 A at the typical supply voltage is a good starting point. Δi_{L} = (1/5 to 2/5) × I_{OUT}. The peak-to-peak inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14 with the typical input voltage used as V_{IN}.
Equation 13.
Equation 14.
D is the duty cycle of the converter which in a buck converter it can be approximated as D = V_{OUT } / V_{IN}, assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro Henries. The inductor ripple current ratio is defined by:
Equation 15.
The second criterion is the inductor saturation current rating. The inductor must be rated to handle the maximum load current plus the ripple current:
Equation 16. I_{L-PEAK} = I_{LOAD-MAX} + Δ i_{L}
The LM46000-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. Enough inductor current ripple improves signal-to-noise ratio on the current comparator and makes the control loop more immune to noise.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
For the design example, a standard 27-μH inductor from Würth, Coiltronics, or Vishay can be used for the 3.3 V output with plenty of current rating margin.
8.2.2.6 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output capacitance as possible to keep cost and size down. Chose the output capacitor (s), C_{OUT}, with care since it directly affects the steady-state output voltage ripple, loop stability and the voltage over/undershoot during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the ESR of the output capacitors:
Equation 17. ΔV_{OUT-ESR} = Δi_{L}× ESR
The other is caused by the inductor current ripple charging and discharging the output capacitors:
Equation 18. ΔV_{OUT-C} = Δi_{L}/ ( 8 × F_{S} × C_{OUT} )
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens, output capacitors provide the required charge before the inductor current can slew to the appropriate level. The initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until the control loop response increases or decreases the inductor current to supply the load. To maintain a small over- or under-shoot during a transient, small ESR and large capacitance are desired. But these also come with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage deviation.
For a given input and output requirement, Equation 19 gives an approximation for an absolute minimum output capacitor required:
Equation 19.
Along with this for the same requirement, calculate the maximum ESR per Equation 20
Equation 20.
where
- r = ripple ratio of the inductor ripple current (ΔI_{L} / I_{OUT})
- ΔV_{OUT} = target output voltage undershoot
- D’ = 1 – duty cycle
- F_{S} = switching frequency
- I_{OUT} = load current
A general guideline for C_{OUT} range is that C_{OUT} must be larger than the minimum required output capacitance calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In applications with V_{OUT} less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit potential output voltage overshoots as the input voltage falls below the device normal operating range. To optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback resistor. For this design example, two 47-µF, 10-V, X7R ceramic capacitors are used in parallel.
8.2.2.7 Feed-Forward Capacitor
The LM46000-Q1 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively. Depending on the V_{OUT} and frequency F_{S}, if the output capacitor C_{OUT} is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor C_{FF} can be added in parallel with R_{FBT}. C_{FF} is chosen such that phase margin is boosted at the crossover frequency without C_{FF}. A simple estimation for the crossover frequency without C_{FF} (f_{x}) is shown in Equation 21, assuming C_{OUT} has very small ESR.
Equation 21.
Equation 22 for C_{FF} was tested:
Equation 22.
Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies caused by the C_{FF} capacitor.
For designs with higher ESR, C_{FF} is not needed when C_{OUT} has very high ESR and C_{FF} calculated from Equation 22 must be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 33-pF COG capacitor is selected.
8.2.2.8 Bootstrap Capacitors
Every LM46000-Q1 design requires a bootstrap capacitor, C_{BOOT}. The recommended bootstrap capacitor is 0.47 μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
8.2.2.9 VCC Capacitor
The VCC pin is the output of an internal LDO for LM46000-Q1. The input for this LDO comes from either VIN or BIAS (see Functional Block Diagram for LM46000-Q1). To insure stability of the part, place a minimum of 2.2-µF, 10-V capacitor from this pin to ground.
8.2.2.10 BIAS Capacitors
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO is internally connected into VIN. Because this is an LDO, the voltage differences between the input and output affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS pin as an input capacitor for the LDO.
8.2.2.11 Soft-Start Capacitors
The user can leave the SS/TRK pin floating, and the LM46000-Q1 implement a soft-start time of 4.1 ms typically. In order to use an external soft-start capacitor, the capacitor must be sized such that the soft-start time is longer than 4.1 ms. Use Equation 23 to calculate the soft start capacitor value:
Equation 23.
where
- C_{SS} = soft-start capacitor value (µF)
- I_{SS} = soft-start charging current (µA)
- t_{SS} = desired soft-start time (s)
For the desired soft start time of 10 ms and soft-start charging current of 2.2 µA, Equation 23 yields a soft-start capacitor value of 0.022 µF.
8.2.2.12 Undervoltage Lockout Setpoint
The UVLO is adjusted using the external voltage divider network of R_{ENT} and R_{ENB}. R_{ENT} is connected between VIN and the EN pin of the LM46000-Q1 device. R_{ENB} is connected between the EN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. Equation 24 can be used to determine the rising VIN (UVLO) level:
Equation 24. V_{IN-UVLO-RISING} = V_{ENH} × (R_{ENB} + R_{ENT}) / R_{ENB}
The EN rising threshold for LM46000-Q1 is set to be 2.1 V. Choose the value of R_{ENB} to be 1 MΩ to minimize input current going into the converter. If the desired VIN (UVLO) level is at 5 V, then the value of R_{ENT} can be calculated using the Equation 25:
Equation 25. R_{ENT} = (V_{IN-UVLO-RISING} / V_{ENH} – 1) × R_{ENB}
Equation 25 yields a value of 1.37 MΩ. The resulting falling UVLO threshold can be calculated as follows:
Equation 26. V_{IN-UVLO-FALLING} = 1.8 × (R_{ENB} + R_{ENT}) / R_{ENB}
8.2.2.13 PGOOD
A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.