SNVS397E September   2005  – November 2016 LM5005

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Voltage Start-Up Regulator
      2. 7.3.2 Shutdown and Standby
      3. 7.3.3 Oscillator and Synchronization Capability
      4. 7.3.4 Error Amplifier and PWM Comparator
      5. 7.3.5 RAMP Generator
      6. 7.3.6 Current Limit
      7. 7.3.7 Soft-Start Capability
      8. 7.3.8 MOSFET Gate Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Light-Load Operation
      4. 7.4.4 Thermal Shutdown Protection
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reducing Bias Power Dissipation
      2. 8.1.2 Input Voltage UVLO Protection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Frequency Set Resistor (RT)
        2. 8.2.2.2  Inductor (LF)
        3. 8.2.2.3  Ramp Capacitor (CRAMP)
        4. 8.2.2.4  Output Capacitors (COUT)
        5. 8.2.2.5  Schottky Diode (DF)
        6. 8.2.2.6  Input Capacitors (CIN)
        7. 8.2.2.7  VCC Capacitor (CVCC)
        8. 8.2.2.8  Bootstrap Capacitor (CBST)
        9. 8.2.2.9  Soft Start Capacitor (CSS)
        10. 8.2.2.10 Feedback Resistors (RFB1 and RFB2)
        11. 8.2.2.11 RC Snubber (RS and CS)
        12. 8.2.2.12 Compensation Components (RC1, CC1, CC2)
        13. 8.2.2.13 Bill of Materials
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout for EMI Reduction
      2. 10.1.2 Thermal Design
      3. 10.1.3 Ground Plane Design
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
        1. 11.3.1.1 PCB Layout Resources
        2. 11.3.1.2 Thermal Design Resources
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Reducing Bias Power Dissipation

The LM5005 is a wide input voltage range buck regulator with a maximum output current of 2.5 A. In general, buck regulators operating at high input voltage can dissipate a significant amount of bias power. The VCC regulator must step-down the input voltage to a nominal VCC level of 7 V. A large voltage drop across the VCC regulator implies a large power dissipation in the LM5005. There are several techniques that can significantly reduce this bias regulator power dissipation.

Figure 14 and Figure 15 depict two methods to bias the IC from the output voltage. In each case the internal VCC regulator is used to initially bias the VCC rail. After the output voltage is established, the voltage at VCC is raised above the nominal 7-V regulation level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin must never exceed 14 V. The voltage at the VCC pin must not exceed the input voltage, VIN.

LM5005 VCC_bias_schematic_nvs397.gif Figure 14. VCC Bias From the Output Voltage for 8 V < VOUT < 14 V
LM5005 Winding_bias_schematic_nvs397.gif Figure 15. VCC Bias Using an Additional Winding on the Buck Inductor

Given the increased gate drive capability with a higher VCC voltage, use a resistor RBST of 5 Ω to 10 Ω in series with the bootstrap capacitor to reduce the turnon speed of the power MOSFET and curtail SW node voltage overshoot and ringing.

Input Voltage UVLO Protection

The SD input supports adjustable input voltage undervoltage lockout (UVLO) with hysteresis for application specific power-up and power-down requirements. SD connects to a comparator-based input referenced to a 1.225-V bandgap voltage with 100-mV hysteresis. An external logic signal can be used to drive the SD input to toggle the output ON and OFF and for system sequencing or protection.

LM5005 UVLO_schematic_nvs397.gif Figure 16. Programmable Input Voltage UVLO With Hysteresis

If the SD pin is not used, it can be left open circuit as it is pulled high by an internal 5-µA current source. This allows self-start-up of the LM5005 when VCC is within its valid operating range above its UVLO threshold. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 16 to establish a precision input voltage UVLO level.

Given VIN(on) and VIN(off) as the input voltage turnon and turnoff thresholds, respectively, select the UVLO resistors using Equation 7 and Equation 8.

Equation 7. LM5005 q_Ruv1_nvs397.gif
Equation 8. LM5005 q_Ruv2_nvs397.gif

An optional capacitor CUV in parallel with RUV2 provides filtering for the divider. If the input UVLO level is set at a low input voltage, it is possible that the maximum SD pin voltage of 7 V could be exceeded at the higher end of the input voltage operating range. In this case, use a small 6.2-V Zener diode clamp from SD to AGND such that the maximum SD operating voltage is never exceeded.

Typical Application

The following design procedure assists with component selection for the LM5005. Alternately, the WEBENCH® Design Tool is available to generate a complete design. With access to a comprehensive component database, this online tool uses an iterative design procedure to create an optimized design, allowing the user to experiment with various design options.

The schematic diagram of a 5-V, 2.5-A regulator with an input voltage range is 7 V to 75 V is given in Figure 17. The free-running switching frequency (with the SYNC pin open circuit) is 300 kHz. In terms of control loop performance, the target loop crossover frequency is 20 kHz with a phase margin in excess of 55°.

LM5005 LM5005_app1_schematic_nvs397.gif Figure 17. LM5005 Circuit Schematic

Design Requirements

An example of the step-by-step procedure to generate power stage and compensation component values using the typical application setup of Figure 17 is given below.

The circuit shown in Figure 17 is configured for the following specifications:

  • VIN = 7 V to 75 V
  • VOUT = 5 V
  • IOUT(max) = 2.5 A
  • FSW = 300 kHz
  • Minimum load current for CCM = 250 mA
  • Line and load regulation less than 1% and 0.1%, respectively

The Bill of Materials for this design is listed in Table 1.

Detailed Design Procedure

Frequency Set Resistor (RT)

Resistor RT sets the switching frequency. Generally, higher frequency applications are smaller but have higher losses. A switching frequency of 300 kHz is selected in this example as a reasonable compromise for small solution size and high efficiency. Calculate the resistance of RT for a 300-kHz switching frequency with Equation 9.

Equation 9. LM5005 q_Rt_nvs397.gif

Choose the nearest standard resistor value of 20.5 kΩ for RT.

Inductor (LF)

The inductance is determined based on the switching frequency, load current, inductor ripple current, and the minimum and maximum input voltages designated VIN(min) and VIN(max), respectively.

LM5005 Current_Waveform_nvs397.gif Figure 18. Inductor Current Waveform

To keep the converter operating in CCM, the maximum inductor ripple current ΔIL must be less than twice the minimum load current, or 0.5-A peak-to-peak. Using this value of ripple current, calculate the inductance using Equation 10.

Equation 10. LM5005 q_Lf_nvs397.gif

Use the nearest standard value of 33 µH. An alternative method is to choose an inductance that gives an inductor ripple current of 30% to 50% of the rated full load current at the nominal input voltage.

Note that the inductor must be rated for the peak inductor current, denoted as IPEAK in Figure 18, to prevent saturation. During normal loading conditions, the peak inductor current corresponds to maximum load current plus half the maximum peak-to-peak ripple current. The peak inductor current during an overload condition is limited to 3.5 A nominal (4.25 A maximum). The selected inductor in this design example (see Table 1) has a conservative 6.2-A saturation current rating. The saturation current is defined by this inductor manufacturer as the current required for the inductance to reduce by 30% at 20°C.

Ramp Capacitor (CRAMP)

With the inductor selected, calculate the value of CRAMP necessary for the emulation ramp circuit using Equation 11.

Equation 11. LM5005 q_Cramp_nvs397.gif

With LF selected as 33 µH, the recommended CRAMP is 330 pF. Use a capacitor with NP0 or C0G dielectric.

Output Capacitors (COUT)

The output capacitor filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM5005 that provide various advantages. The best performance is typically obtained using ceramic or polymer electrolytic type components. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while electrolytic capacitors provide a large bulk capacitance in a small volume for transient loading conditions.

When selecting an output capacitor, the two performance characteristics to consider are the output voltage ripple and load transient response. Approximate the output voltage ripple with Equation 12.

Equation 12. LM5005 q_delta_Vout_nosb87.gif

where

  • ΔVOUT is the peak-to-peak output voltage ripple
  • RESR is the effective series resistance (ESR) of the output capacitor
  • FSW is the switching frequency
  • COUT is the effective output capacitance

The amount of output voltage ripple is application specific. A general recommendation is to keep the output ripple less than 1% of the rated output voltage.

Bear in mind that ceramic capacitors are sometimes preferred because they have low ESR. However, depending on package and voltage rating of the capacitor, the effective in-circuit capacitance can drop significantly with applied voltage. The output capacitor selection also affects the output voltage droop during a load transient. The peak deviation of the output voltage during a load transient is dependent on many factors. An approximation of the transient dip ignoring loop bandwidth is obtained using Equation 13:

Equation 13. LM5005 q_Vdroop_nosb87.gif

where

  • COUT is the minimum required output capacitance
  • LF is the buck filter inductance
  • VDROOP is the output voltage deviation ignoring loop bandwidth considerations
  • ΔIOUT-STEP is the load step change
  • RESR is the output capacitor ESR
  • VIN is the input voltage
  • VOUT is the output voltage setpoint

A 22-µF, 16-V ceramic capacitor with X7R dielectric and 1210 footprint and a 150-µF, 6.3-V polymer electrolytic capacitor are selected here based on a review of each capacitor's tolerance and voltage coefficient to meet output ripple specification. The ceramic capacitor provides ultra-low ESR to reduce the output ripple voltage and noise spikes, while the electrolytic capacitor provides a large bulk capacitance in a small volume for transient loading conditions.

Schottky Diode (DF)

A Schottky type freewheeling diode is required for all LM5005 applications. Select the diode's reverse breakdown rating for the maximum VIN plus some safety margin. Ultra-fast diodes are not recommended and may result in damage to the regulator due to reverse recovery current transients. The near ideal reverse recovery characteristics and low forward voltage drop of a Schottky diode are particularly important diode characteristics for high input voltage and low output voltage applications common to the LM5005.

The reverse recovery characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The benign reverse recovery characteristics of a Schottky diode minimizes the peak instantaneous power in the buck switch occurring during turnon each cycle, and the resulting switching losses of the buck switch are significantly reduced.

The diode's forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a low output voltage. Rated current for diodes vary widely from various manufactures. The worst case is to assume a short-circuit load condition. In this case the diode conducts the output current almost continuously. For the LM5005 this current can be as high as 3.5 A. Assuming a worst-case 1-V drop across the diode, the maximum diode power dissipation can be as high as 3.5 W. For this design example, a 100-V, 6-A Schottky in a DPAK package is selected.

Input Capacitors (CIN)

The regulator supply voltage has a large source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the buck switch turns on, the current into the VIN pins steps to the lower peak of the inductor current waveform, ramps up to the peak value, then drops to zero at turnoff. The average current into VIN during the on-time is the load current. The input capacitance must be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.

Select ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage derating effects, two 2.2-µF, 100-V ceramic capacitors are used. If step input voltage transients are expected near the maximum rating of the LM5005, a careful evaluation of ringing and possible spikes at the VIN pin id required. An additional damping network, snubber circuit or input voltage clamp may be required in these cases.

VCC Capacitor (CVCC)

The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value of CVCC is 0.47 µF and must be a low-ESR ceramic capacitor of X7R dielectric rated for at least 16 V.

Bootstrap Capacitor (CBST)

The bootstrap capacitor connected between the BST and SW pins supplies the gate current to charge the buck switch gate at turnon. The recommended value of CBST is 22 nF. Choose a low ESR ceramic capacitor with X7R dielectric rated for at least 16 V.

Soft Start Capacitor (CSS)

The capacitor connected to the SS pin determines the soft-start time, or the time for the reference voltage and the output voltage to reach their final regulated values. If tSS is the required soft-start time, calculate the soft-start capacitance using Equation 14 or more simply with Equation 15.

Equation 14. LM5005 q_Css_nvs397.gif
Equation 15. LM5005 q_Css_simplified_nvs397.gif

Choose a CSS of 10 nF corresponding to a soft-start time of 1.2 ms for this application.

Feedback Resistors (RFB1 and RFB2)

Resistors RFB1 and RFB2 establish the output voltage setpoint. Based on a selected value for the lower feedback resistor RFB2, calculate the upper feedback resistor RFB1 from Equation 16.

Equation 16. LM5005 q_RFBB_nvs397.gif

In general, a good starting point for RFB2 is in the range of 1 kΩ to 10 kΩ. Resistances of 5.11 kΩ and 1.65 kΩ are selected for RFB1 and RFB2 (respectively) to achieve a 5-V output setpoint for this design example.

RC Snubber (RS and CS)

A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Ultimately, excessive spikes beyond the rating of the LM5005 or the freewheeling diode can damage these devices. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are short. For the current levels typical of the LM5005 converter, a snubber resistance RS between
2 Ω and 10 Ω is adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a minimum value of CS that provides adequate damping of the SW voltage waveform at full load (see PCB Layout for EMI Reduction for more details).

Compensation Components (RC1, CC1, CC2)

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current-mode control is the ability to close the loop with only two feedback components, RC1 and CC1. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM5005 is calculated with Equation 17.

Equation 17. LM5005 q_DC_Gain_nvs397.gif

The dominant low-frequency pole of the modulator is determined by the load resistance, RLOAD, and the output capacitance, COUT. Calculate the corner frequency of this pole with Equation 18.

Equation 18. LM5005 q_fp_mod_nvs397.gif

For RLOAD = 5 Ω and COUT = 177 µF, then fp(MOD) = 180 Hz

GAINMOD-DC = 2 A/V × 5 Ω = 10 = 20 dB

For this design example given RLOAD = 5 Ω and COUT = 177 µF, Figure 19 shows the experimentally measured modulator gain versus frequency characteristic.

LM5005 20161915.gif Figure 19. PWM Modulator Gain and Phase Plot

Components RC1 and CC1 configure the error amplifier as a Type-II configuration, giving a pole at the origin and a zero at fZ = 1 / (2π RC1 CC1). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a stable loop with 90° of phase margin.

For the design example, select a target loop bandwidth (crossover frequency) of 20 kHz. Place the compensator zero frequency, fZ, an order of magnitude less than the target crossover frequency. This constrains the product of RC1 and CC1 for a desired compensation network zero frequency to be less than 2 kHz. Increasing RC1 while proportionally decreasing CC1 increases the error amp gain. Conversely, decreasing RC1 while proportionally increasing CC1, decreases the error amp gain. Select RC1 of 49.9 kΩ and CC1 of 10 nF. These values configure the compensation network zero at 320 Hz. The compensator gain at frequencies greater than fZ is RC1 / RFB1, which is approximately 20 dB.

The compensator's bode plot is shown by Figure 20. The overall loop is predicted as the sum (in dB) of the modulator gain and the compensator gain as shown in Figure 21.

LM5005 20161916.gif Figure 20. Compensator Gain and Phase Plot
LM5005 20161917.gif Figure 21. Overall Loop Gain and Phase Plot

If a network analyzer is available, measure the modulator gain and configure the compensator gain for the desired loop transfer function. If a network analyzer is not available, design the error amplifier's compensation components using the guidelines provided. Perform step-load transient tests to verify acceptable performance. The step load goal is minimum overshoot with a damped response. Add a capacitor CC2 to the compensation network to decrease noise susceptibility of the error amplifier. The value of CC2 must be sufficiently small, because the addition of this capacitor adds a pole in the compensator transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by CC2 is Equation 19.

Equation 19. fp2 = fZ × CC1 / CC2

An alternative method to decrease the error amplifier noise susceptibility is to connect a capacitor from COMP to AGND. When using this method, the capacitance of CC2 must not exceed 100 pF.

Bill of Materials

Table 1 lists the bill of materials for the design example.

Table 1. LM5005 Buck Regulator Bill of Materials(1), VOUT = 5 V, IOUT = 2.5 A

REF DES DESCRIPTION VENDOR PART NUMBER QUANTITY
CIN1, CIN2 CAPACITOR, CER, 2.2 µF, 100 V, X7R, 1210 TDK C3225X7R2A225M 2
COUT1 CAPACITOR, SP, 150 µF, 6.3 V, 12 mΩ Panasonic EEFHE0J151R 1
COUT2 CAPACITOR, CER, 22 µF, 16 V, X7R, 1210 TDK C3225X7R1C226M 1
CS CAPACITOR, CER, 330 pF, 100 V, 0603 Kemet C0603C331G1GAC 1
CC1, CSS CAPACITOR, CER, 10 nF, 100 V, 0603 TDK C1608X7R2A103K 2
CBST CAPACITOR, CER, 22 nF, 100 V, 0603 TDK C1608X7R2A223K 1
CVCC CAPACITOR, CER, 0.47 µF, 16 V, 0604 TDK C1608X7R1C474M 1
CRAMP CAPACITOR, CER, 330 pF, 100 V, 0603 Kemet C0603C331G1GAC 1
DF DIODE, 100 V, 6 A, Schottky, DPAK Central Semi CSHD6-100C 1
DIODE, 100 V, 6 A, Schottky (alternative) IR 6CWQ10FN
LF INDUCTOR, 33 µH, ISAT 6.22 A, DCR 60 mΩ Coiltronics/Eaton DR127-330-R 1
RT RESISTOR, 20.5 kΩ, 0603 Vishay Dale CRCW06032052F 1
RC1 RESISTOR, 49.9 kΩ, 0603 Vishay Dale CRCW06034992F 1
RFB1 RESISTOR, 5.11 kΩ, 0603 Vishay Dale CRCW06035111F 1
RFB2 RESISTOR, 1.65 kΩ, 0603 Vishay Dale CRCW06031651F 1
RS RESISTOR, 10 Ω, 1 W, 1206 Vishay Dale CRCW1206100J 1
U1 Wide VIN Regulator, 75 V, 2.5 A Texas Instruments LM5005 1

Application Curves

Converter efficiency and performance waveforms are shown from Figure 22 to Figure 32. Unless indicated otherwise, all waveforms are taken at VIN = 48 V.

LM5005 D001SNVS397E.gif Figure 22. Typical Efficiency vs Input Voltage
and Output Current, 5-V Output
LM5005 VOUTripple_nvs397.gif Figure 23. Output Voltage Ripple, 2.5-A Load
LM5005 SW_48Vin_nvs397.gif Figure 24. SW Node Voltage, 2.5-A Load
LM5005 EnableON_nvs397.gif Figure 26. Start-Up Using SD Pin, 2.5-A Resistive Load
LM5005 EnableON_prebias_nvs397.gif Figure 28. Start-Up Using SD Pin, Pre-biased Output
LM5005 Load_transient1_nvs397.gif Figure 30. Load Transient Response, 0.1-A to 2.5-A Load
LM5005 LineTransientRising_nvs397.gif Figure 32. Line Transient, 12 V to 60 V, 2.5-A Load
LM5005 SW_48Vin_0.1Aout_nvs397.gif Figure 25. SW Node Voltage, 0.1-A Load
LM5005 EnableOFF_nvs397.gif Figure 27. Shutdown Using SD Pin, 2.5-A Resistive Load
LM5005 Startup_nvs397.gif Figure 29. Start-Up by Applying VIN, 2.5-A Resistive Load
LM5005 Load_transient2_nvs397.gif Figure 31. Load Transient Response, 1.25-A to 2.5-A Load
LM5005 SYNC_48Vin_nvs397.gif Figure 33. SYNC IN Operation at 350 kHz