SNVSAG9 March   2016 LM5022-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5022-Q1
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage Start-Up Regulator
      2. 7.3.2 Input Undervoltage Detector
      3. 7.3.3 Error Amplifier
      4. 7.3.4 Current Sensing and Current Limiting
      5. 7.3.5 PWM Comparator and Slope Compensation
      6. 7.3.6 Soft Start
      7. 7.3.7 MOSFET Gate Driver
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Oscillator, Shutdown, and SYNC
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  MOSFET
        3.  Output Diode
        4.  Boost Inductor
        5.  Output Capacitor
        6.  VCC Decoupling Capacitor
        7.  Input Capacitor
        8.  Current Sense Filter
        9.  RSNS, RS2 and Current Limit
        10. Control Loop Compensation
        11. Efficiency Calculations
          1. Chip Operating Loss
          2. MOSFET Switching Loss
          3. MOSFET and RSNS Conduction Loss
          4. Output Diode Loss
          5. Input Capacitor Loss
          6. Output Capacitor Loss
          7. Boost Inductor Loss
          8. Total Loss
          9. Efficiency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Filter Capacitors
      2. 10.1.2 Sense Lines
      3. 10.1.3 Compact Layout
      4. 10.1.4 Ground Plane and Shape Routing
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Design Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To produce an optimal power solution with the LM5022-Q1, good layout and design of the PCB are as critical as component selection. The following are the several guidelines in order to create a good layout of the PCB, as based on Figure 15.

  1. Using a low ESR ceramic capacitor, place CINX as close as possible to the VIN and GND pins of the LM5022-Q1.
  2. Using a low ESR ceramic capacitor, place COX close to the load as possible of the LM5022-Q1
  3. Using a low ESR ceramic capacitor place CF close to the VCC and GND pins of the LM5022-Q1
  4. Minimize the loop area formed by the output capacitor connections (Co1, Co2 ), by D1 and Rsns. Making sure the cathode of D1 and Rsns are position next to each other and place Co1(+ )and Co1( -) close to D1 cathode and Rsns (-) respectively.
  5. Rsns (+) should be connected to the CS pin with a separate trace made as short as possible. This trace should be routed away from the inductor and the switch node (where D1, Q1, and L1 connect).
  6. Minimize the trace length to the FB pin by positioning RFB1 and RFB2 close to the LM5022-Q1
  7. Route the VOUT sense path away from noisy node and connect it as close as possible to the positive side of COX.

10.1.1 Filter Capacitors

The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter, is minimized. Place CINX as close as possible to the VIN and GND pins of the LM5022-Q1. Place COX close to the load, and CF next to the VCC and GND pins of the LM5022-Q1.

10.1.2 Sense Lines

The top of RSNS should be connected to the CS pin with a separate trace, made as short as possible. Route this trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep RFB1and RFB2 close to the LM5022-Q1 and run a trace, as close as possible, to the positive side of COX to RFB2. As with the CS line, the FB line should be routed away from the inductor and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup.

10.1.3 Compact Layout

  1. Parasitic inductance can be reduced by keeping the power path components close together. As described above in point 4 in the Layout Guidelines, keep the high slew-rate current loops as tight as possible. Short, thick traces or copper pours (shapes) are best
  2. The switch node should be just large enough to connect all the components together without excessive heating from the current it carries. The LM5022-Q1 (boost converter) operates in two distinct cycles whose high current paths are shown in Figure 30:

LM5022-Q1 20212252.gif Figure 30. Boost Converter Current Loops

The dark grey, inner loops represent the high current paths during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time.

10.1.4 Ground Plane and Shape Routing

The diagram of Figure 30 is useful for analyzing the flow of continuous current vs. the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the MOSFET and the path between the output capacitor and the load are examples of continuous current paths. In contrast, the path between the grounded side of the power switch and the negative output capacitor terminal carries a large high slew-rate pulsating current. This path should be routed with a short, thick shape, preferably on the component side of the PCB. Too keep the parasitic inductance low, multiple vias in parallel should be placed on the negative pads of the input and output capacitors to connect the component side to the ground plane. Vias should not be placed directly at the grounded side of the MOSFET (or RSNS) as they tend to inject noise into the ground plane. A second pulsating current loop is the gate drive loop formed by the OUT and VCC pins, Q1, RSNS and capacitor CF. These loops must be kept small.

10.2 Layout Example

LM5022-Q1 Layout1.gif Figure 31. Typical Top Layer Overlay of the LM5022 Evaluation Board
LM5022-Q1 Layout2.gif Figure 32. Typical Bottom Layer Overlay of the LM5022 Evaluation Board