SNVSB51C September 2018 – December 2025 LM5164-Q1
PRODUCTION DATA
Figure 4-1 DDA Package 8-Pin SO PowerPAD™
Integrated Circuit Package (Top View)| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | GND | G | Ground connection for internal circuits |
| 2 | VIN | P/I | Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly to the input supply of the buck converter with short, low impedance paths. |
| 3 | EN/UVLO | I | Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is greater than 1.1V and below 1.5V, the converter is in standby mode with the internal VCC regulator operational and no switching. If the EN/UVLO voltage is above 1.5V, the start-up sequence begins. |
| 4 | RON | I | On-time programming pin. A resistor between this pin and GND sets the buck switch on-time. |
| 5 | FB | I | Feedback input of voltage regulation comparator |
| 6 | PGOOD | O | Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an external pullup resistor between 10kΩ to 100kΩ. |
| 7 | BST | P/I | Bootstrap gate-drive supply. Required to connect a high-quality 2.2nF 50V X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
| 8 | SW | P | Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. |
| — | EP | — | Exposed pad of the package. No internal electrical connection. Connect the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. |