SNVSA37A October   2015  – May 2016 LM5175


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 8.3.2  VCC Regulator and Optional BIAS Input
      3. 8.3.3  Enable/UVLO
      4. 8.3.4  Soft-Start
      5. 8.3.5  Overcurrent Protection
      6. 8.3.6  Average Input/Output Current Limiting
      7. 8.3.7  CCM/DCM Operation
      8. 8.3.8  Frequency and Synchronization (RT/SYNC)
      9. 8.3.9  Frequency Dithering
      10. 8.3.10 Output Overvoltage Protection (OVP)
      11. 8.3.11 Power Good (PGOOD)
      12. 8.3.12 Gm Error Amplifier
      13. 8.3.13 Integrated Gate Drivers
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown, Standby, and Operating Modes
      2. 8.4.2 MODE Pin Configuration
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Custom Design with WEBENCH Tools
        2.  Frequency
        3.  VOUT
        4.  Inductor Selection
        5.  Output Capacitor
        6.  Input Capacitor
        7.  Sense Resistor (RSENSE)
        8.  Slope Compensation
        9.  UVLO
        10. Soft-Start Capacitor
        11. Dither Capacitor
        12. MOSFETs QH1 and QL1
        13. MOSFETs QH2 and QL2
        14. Frequency Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design with WEBENCH Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The basic PCB board layout requires separation of sensitive signal and power paths. The following checklist should be followed to get good performance for a well designed board.

  • Place the power components including the input filter capacitor CIN, the power MOSFETs QL1 and QH1, and the sense resistor RSENSE close together to minimize the loop area for input switching current in buck operation.
  • Place the power components including the output filter capacitor COUT, the power MOSFETs QL2 and QH2, and the sense resistor RSENSE close together to minimize the loop area for output switching current in boost operation.
  • Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the input and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high di/dt switching currents.
  • Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.
  • Layout the gate drive traces and return paths as directly as possible. Layout the forward and return traces close together, either running side by side or on top of each other on adjacent layers to minimize the inductance of the gate drive path.
  • Use Kelvin connections to RSENSE for the current sense signals CS and CSG and run lines in parallel from the RSENSE terminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 nodes or high-side gate drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible.
  • Place the CIN, COUT, and RSENSE ground pins as close as possible with thick ground trace and/or planes on multiple layers.
  • Place the VCC bypass capacitor close to the controller IC, between the VCC and PGND pins. A 1-µF ceramic capacitor is typically used.
  • Place the BIAS bypass capacitor close to the controller IC, between the BIAS and PGND pins. A 0.1-µF ceramic capacitor is typically used.
  • Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins.
  • Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins.
  • Bypass the VIN pin to AGND with a low ESR ceramic capacitor located close to the controller IC. A 0.1 µF ceramic capacitor is typically used. When using external BIAS, use a diode between input rails and VIN pins to prevent reverse conduction when VIN < VCC.
  • Connect the feedback resistor divider between the COUT positive terminal and AGND pin of the IC. Place the components close to the FB pin.
  • Use care to separate the power and signal paths so that no power or switching current flows through the AGND connections which can either corrupt the COMP, SLOPE, or SYNC signals, or cause dc offset in the FB sense signal. The PGND and AGND traces can be connected near the PGND pin, near the VCC capacitor PGND connection, or near the PGND connection of the CS, CSG pin current sense resistor.
  • When using the average current loop, divide the overall capacitor (CIN or COUT) between the two sides of the sense resistor to ensure small cycle-by-cycle ripple. Place the average current loop filter capacitor close to the IC between the ISNS(+) and ISNS(-) pins.

11.2 Layout Example

LM5175 layout_pwr_stage_snvsa37.gif Figure 29. LM5175 Power Stage Layout