The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitor and power ground, as shown in Figure 46. This loop carries fast transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the converter. Because of this, the traces in this loop should be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Figure 47 shows a recommended layout for the critical components of the LM53603-Q1. This PCB layout is a good guide for any specific application. The following important guidelines should also be followed:
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As mentioned above, it is recommended to use one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pins are connected to the source of the internal low side MOSFET switch. They should be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes.
It is recommended to provide adequate device heat sinking by utilizing the exposed pad (EP) of the IC as the primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the EP to the system ground plane for heat sinking. The vias should be evenly distributed under the exposed pad. Use as much copper as possible for system ground plane on the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer board with the copper thickness, starting from the top, as: 2 oz / 1 oz / 1 oz / 2 oz. A four layer board with enough copper thickness and proper layout provides low current conduction impedance, proper shielding and lower thermal resistance.
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